From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 98012 invoked by alias); 24 May 2015 08:50:54 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 97996 invoked by uid 48); 24 May 2015 08:50:49 -0000 From: "gccbugs at rooted dot tk" To: gcc-bugs@gcc.gnu.org Subject: [Bug ipa/66271] New: -Os generates incorrect code on ARM possibly due to IPA Date: Sun, 24 May 2015 08:50:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: ipa X-Bugzilla-Version: 5.1.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: major X-Bugzilla-Who: gccbugs at rooted dot tk X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone attachments.created Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-05/txt/msg02010.txt.bz2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66271 Bug ID: 66271 Summary: -Os generates incorrect code on ARM possibly due to IPA Product: gcc Version: 5.1.0 Status: UNCONFIRMED Severity: major Priority: P3 Component: ipa Assignee: unassigned at gcc dot gnu.org Reporter: gccbugs at rooted dot tk Target Milestone: --- Created attachment 35609 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35609&action=edit code snippet and generated assembly GCC generates incorrect code when cross compiling for ARM on x86_64 on version 5.1.0 snapshot 5-20150519. The code is correct when -fno-ipa-sra is added as a switch, making me believe that this is an issue with IPA. This bug breaks compiling Linux, particularly lib/vsprintf.c. The problematic part of that file is attached as a code snippet along with the generated assembly. It was compiled with the following command line: arm-none-eabi-gcc bug.c -S -o bug.s -Os -Wall -Wextra -fverbose-asm -frecord-gcc-switches The issue occurs if spec.field_width is passed in as -1. LDRSH at line 96 correctly sign extends this 16-bit value to the 32-bit value -1. If !(spec.flags & LEFT), then the branch at line 100 is not taken. The loop does not run due to the comparison at line 104 (r0 is the result of strnlen(s, ...)). However, lines 103 and 105 effectively zero out the top 16 bits of r3, which is later written back to r5 at line 114. At line 132, r5 should be -2 or 0xFFFFFFFE but is instead 0x0000FFFE. Thus, the branch at line 136 is not taken even though it should not be taken ((len < spec.field_width--) should always be true if spec.field_width is negative and no wrapping occurs). The end result is that lines 49-51 in the C file run once even when they should not run. The code would work correctly if LSR were replaced with ASR on lines 105 and 135. This is done correctly at lines 110 and 140, which makes it odd that the other two lines would be different.