[Bug rtl-optimization/66706] New: Redundant shift instruction on x >> (n & 32)

[Bug rtl-optimization/66706] New: Redundant shift instruction on x >> (n & 32)

[msebor at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66706

            Bug ID: 66706
           Summary: Redundant shift instruction on x >> (n & 32)
           Product: gcc
           Version: 5.1.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: enhancement
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: msebor at gcc dot gnu.org
                CC: mpolacek at gcc dot gnu.org, msebor at gcc dot gnu.org,
                    rv at rasmusvillemoes dot dk, segher at gcc dot gnu.org,
                    unassigned at gcc dot gnu.org
        Depends on: 66552
  Target Milestone: ---
            Target: x86, powerpc64

+++ This bug was initially created as a clone of Bug #66552 +++

Compiling the following function with -O2:

        unsigned f(unsigned x, int n)
        {
            return x >> (n & 32);
        }

results in an unnecessary instruction to zero out the already clear high order
bits of register 3 after the shift instruction:

        rldicl 4,4,0,59
        srw 3,3,4
        rldicl 3,3,0,32
        blr

Clang emits an optimal sequence:

        rlwinm 4, 4, 0, 27, 31
        srw 3, 3, 4
        blr


Referenced Bugs:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66552
[Bug 66552] Missed optimization when shift amount is result of signed modulus

[Bug rtl-optimization/66706] Redundant bitmask instruction on x >> (n & 32)

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66706

Segher Boessenkool <segher at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2015-06-30
           Assignee|unassigned at gcc dot gnu.org      |segher at gcc dot gnu.org
     Ever confirmed|0                           |1

--- Comment #1 from Segher Boessenkool <segher at gcc dot gnu.org> ---
For some reason when combining the zero_extend with the lshiftrt,
combine writes it as the equivalent and-of-subreg.  Which doesn't
match any existing backend pattern.

Confirmed; mine.

[Bug rtl-optimization/66706] Redundant bitmask instruction on x >> (n & 32)

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66706

--- Comment #2 from Segher Boessenkool <segher at gcc dot gnu.org> ---
Author: segher
Date: Thu Jul  2 16:27:11 2015
New Revision: 225344

URL: https://gcc.gnu.org/viewcvs?rev=225344&root=gcc&view=rev
Log:
        PR rtl-optimization/66706
        * combine.c (make_compound_operation): If an AND of SUBREG of
        LSHIFTRT does not simplify, see if just the AND of SUBREG does.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/combine.c

[Bug rtl-optimization/66706] Redundant bitmask instruction on x >> (n & 32)

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66706

Segher Boessenkool <segher at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #3 from Segher Boessenkool <segher at gcc dot gnu.org> ---
Fixed on trunk.

[Bug rtl-optimization/66706] Redundant bitmask instruction on x >> (n & 32)

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66706

--- Comment #4 from Segher Boessenkool <segher at gcc dot gnu.org> ---
Author: segher
Date: Fri Jul  3 14:37:26 2015
New Revision: 225382

URL: https://gcc.gnu.org/viewcvs?rev=225382&root=gcc&view=rev
Log:
        PR rtl-optimization/66706
        * gcc.target/powerpc/shift-int.c: New testcase.

Added:
    trunk/gcc/testsuite/gcc.target/powerpc/shift-int.c
Modified:
    trunk/gcc/testsuite/ChangeLog

[Bug rtl-optimization/66706] Redundant bitmask instruction on x >> (n & 32)

[guojiufu at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66706
Bug 66706 depends on bug 66552, which changed state.

Bug 66552 Summary: Missed optimization when shift amount is result of signed modulus
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66552

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED