From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugs-return-491061-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org>
Received: (qmail 395 invoked by alias); 30 Jun 2015 15:49:20 -0000
Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm
Precedence: bulk
List-Id: <gcc-bugs.gcc.gnu.org>
List-Archive: <http://gcc.gnu.org/ml/gcc-bugs/>
List-Post: <mailto:gcc-bugs@gcc.gnu.org>
List-Help: <mailto:gcc-bugs-help@gcc.gnu.org>
Sender: gcc-bugs-owner@gcc.gnu.org
Received: (qmail 130835 invoked by uid 48); 30 Jun 2015 15:49:16 -0000
From: "msebor at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/66706] New: Redundant shift instruction on x >> (n & 32)
Date: Tue, 30 Jun 2015 15:49:00 -0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: new
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: rtl-optimization
X-Bugzilla-Version: 5.1.0
X-Bugzilla-Keywords: missed-optimization
X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: msebor at gcc dot gnu.org
X-Bugzilla-Status: UNCONFIRMED
X-Bugzilla-Resolution:
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org
X-Bugzilla-Target-Milestone: ---
X-Bugzilla-Flags:
X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status keywords bug_severity priority component assigned_to reporter cc dependson target_milestone cf_gcctarget
Message-ID: <bug-66706-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: 7bit
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
X-SW-Source: 2015-06/txt/msg03393.txt.bz2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66706

            Bug ID: 66706
           Summary: Redundant shift instruction on x >> (n & 32)
           Product: gcc
           Version: 5.1.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: enhancement
          Priority: P3
         Component: rtl-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: msebor at gcc dot gnu.org
                CC: mpolacek at gcc dot gnu.org, msebor at gcc dot gnu.org,
                    rv at rasmusvillemoes dot dk, segher at gcc dot gnu.org,
                    unassigned at gcc dot gnu.org
        Depends on: 66552
  Target Milestone: ---
            Target: x86, powerpc64

+++ This bug was initially created as a clone of Bug #66552 +++

Compiling the following function with -O2:

        unsigned f(unsigned x, int n)
        {
            return x >> (n & 32);
        }

results in an unnecessary instruction to zero out the already clear high order
bits of register 3 after the shift instruction:

        rldicl 4,4,0,59
        srw 3,3,4
        rldicl 3,3,0,32
        blr

Clang emits an optimal sequence:

        rlwinm 4, 4, 0, 27, 31
        srw 3, 3, 4
        blr


Referenced Bugs:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66552
[Bug 66552] Missed optimization when shift amount is result of signed modulus