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* [Bug target/66776] New: [AArch64] zero-extend version of csel not matching properly
@ 2015-07-06 10:32 ktkachov at gcc dot gnu.org
2015-07-06 10:34 ` [Bug target/66776] " ktkachov at gcc dot gnu.org
2015-10-02 11:55 ` renlin at gcc dot gnu.org
0 siblings, 2 replies; 3+ messages in thread
From: ktkachov at gcc dot gnu.org @ 2015-07-06 10:32 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66776
Bug ID: 66776
Summary: [AArch64] zero-extend version of csel not matching
properly
Product: gcc
Version: 6.0
Status: UNCONFIRMED
Keywords: missed-optimization
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: ktkachov at gcc dot gnu.org
Target Milestone: ---
Consider the code:
unsigned long
foo (unsigned int a, unsigned int b, unsigned int c)
{
return a ? b : c;
}
On aarch64 this generates:
foo:
uxtw x1, w1
cmp w0, wzr
uxtw x2, w2
csel x0, x2, x1, eq
ret
where in fact it could generate:
cmp w0, #0
csel w0, w1, w2, ne
ret
A write to the 32-bit w-register implicitly zero-extends the value up to the
full
64 bits of an x-register.
This is reflected in aarch64.md by the cmovsi_insn_uxtw pattern that matches:
(set (dest:DI)
(zero_extend:DI
(if_then_else:SI (cond) (src1:SI) (src2:SI))
)
)
However, this doesn't get matched because combine instead tries to match
(set (dest:DI)
(if_then_else:DI (cond)
(zero_extend:DI (src1:SI))
(zero_extend:DI (src2:SI))
)
)
As discussed in PR66588 it seems preferable to write the *cmovsi_insn_uxtw
pattern with the zero_extends inside the arms of the if_then_else
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Bug target/66776] [AArch64] zero-extend version of csel not matching properly
2015-07-06 10:32 [Bug target/66776] New: [AArch64] zero-extend version of csel not matching properly ktkachov at gcc dot gnu.org
@ 2015-07-06 10:34 ` ktkachov at gcc dot gnu.org
2015-10-02 11:55 ` renlin at gcc dot gnu.org
1 sibling, 0 replies; 3+ messages in thread
From: ktkachov at gcc dot gnu.org @ 2015-07-06 10:34 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66776
ktkachov at gcc dot gnu.org changed:
What |Removed |Added
----------------------------------------------------------------------------
Target| |aarch64*
Target Milestone|--- |6.0
Known to fail| |6.0
^ permalink raw reply [flat|nested] 3+ messages in thread
* [Bug target/66776] [AArch64] zero-extend version of csel not matching properly
2015-07-06 10:32 [Bug target/66776] New: [AArch64] zero-extend version of csel not matching properly ktkachov at gcc dot gnu.org
2015-07-06 10:34 ` [Bug target/66776] " ktkachov at gcc dot gnu.org
@ 2015-10-02 11:55 ` renlin at gcc dot gnu.org
1 sibling, 0 replies; 3+ messages in thread
From: renlin at gcc dot gnu.org @ 2015-10-02 11:55 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66776
--- Comment #1 from renlin at gcc dot gnu.org ---
Author: renlin
Date: Fri Oct 2 11:55:04 2015
New Revision: 228384
URL: https://gcc.gnu.org/viewcvs?rev=228384&root=gcc&view=rev
Log:
[PATCH][AARCH64][PR66776]Add cmovdi_insn_uxtw pattern.
gcc/
2015-10-02 Renlin Li <renlin.li@arm.com>
PR target/66776
* config/aarch64/aarch64.md (cmovdi_insn_uxtw): New pattern.
gcc/testsuite/
2015-10-02 Renlin Li <renlin.li@arm.com>
PR target/66776
* gcc.target/aarch64/pr66776.c: New.
Added:
trunk/gcc/testsuite/gcc.target/aarch64/pr66776.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/aarch64/aarch64.md
trunk/gcc/testsuite/ChangeLog
^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-07-06 10:32 [Bug target/66776] New: [AArch64] zero-extend version of csel not matching properly ktkachov at gcc dot gnu.org
2015-07-06 10:34 ` [Bug target/66776] " ktkachov at gcc dot gnu.org
2015-10-02 11:55 ` renlin at gcc dot gnu.org
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