[Bug target/67071] New: GCC misses an optimization to load vector constants

[Bug target/67071] New: GCC misses an optimization to load vector constants

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67071

            Bug ID: 67071
           Summary: GCC misses an optimization to load vector constants
           Product: gcc
           Version: 6.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: meissner at gcc dot gnu.org
  Target Milestone: ---
              Host: powerpc64-unknown-linux-gnu
            Target: powerpc64-unknown-linux-gnu
             Build: powerpc64-unknown-linux-gnu

Gcc has a logic error in rs6000.h which prevents it from being able to load
vector constants with the most significant bit set.

The code is:
#define EASY_VECTOR_MSB(n,mode)                                         \
  (((unsigned HOST_WIDE_INT)n) ==                                       \
   ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))

However, if you look at the const_vector that is passed to
easy_altivec_constant, the constant is sign extended, and EASY_VECTOR_MSB would
not match.

If we instead define EASY_VECTOR_MSG to do the mask before doing the comparison
the test will succeed, and the code will generate the vector splat integer
operation followed by vector shift left.

#define EASY_VECTOR_MSB(n,mode)                                         \
  ((((unsigned HOST_WIDE_INT)n) & GET_MODE_MASK (mode)) ==              \
   ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))

A further optimization would be to recognize vector constants where the upper
part can be formed via vector splat integer and then the bottom bits are all 0
or all 1, and we can use VSLDOI instruction with a secondary register that is
all 0's or all 1's.

[Bug target/67071] GCC misses an optimization to load vector constants

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67071

--- Comment #1 from Michael Meissner <meissner at gcc dot gnu.org> ---
Author: meissner
Date: Mon Aug  3 21:52:10 2015
New Revision: 226534

URL: https://gcc.gnu.org/viewcvs?rev=226534&root=gcc&view=rev
Log:
Patch for PR 67071

Added:
    branches/ibm/ieee4/gcc/testsuite/gcc.target/powerpc/pr67071-1.c
    branches/ibm/ieee4/gcc/testsuite/gcc.target/powerpc/pr67071-2.c
    branches/ibm/ieee4/gcc/testsuite/gcc.target/powerpc/pr67071-3.c
Modified:
    branches/ibm/ieee4/gcc/ChangeLog.meissner
    branches/ibm/ieee4/gcc/config/rs6000/altivec.md
    branches/ibm/ieee4/gcc/config/rs6000/predicates.md
    branches/ibm/ieee4/gcc/config/rs6000/rs6000-protos.h
    branches/ibm/ieee4/gcc/config/rs6000/rs6000.c
    branches/ibm/ieee4/gcc/config/rs6000/rs6000.h
    branches/ibm/ieee4/gcc/testsuite/ChangeLog.meissner

[Bug target/67071] GCC misses an optimization to load vector constants

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67071

--- Comment #2 from Michael Meissner <meissner at gcc dot gnu.org> ---
Author: meissner
Date: Wed Aug 12 21:54:23 2015
New Revision: 226836

URL: https://gcc.gnu.org/viewcvs?rev=226836&root=gcc&view=rev
Log:
[gcc]
2015-08-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/67071
        * config/rs6000/predicates.md (easy_vector_constant_vsldoi): New
        predicate to allow construction of vector constants using the
        VSLDOI vector shift instruction.

        * config/rs6000/rs6000-protos.h (vspltis_shifted): Add
        declaration.

        * config/rs6000/rs6000.c (vspltis_shifted): New function to return
        the number of bytes to be shifted left and filled in with either
        all zero or all one bits.
        (gen_easy_altivec_constant): Call vsplitis_shifted if no other
        methods exist.
        (output_vec_const_move): On power8, generate XXLORC to generate
        a vector constant with all 1's. Do a split if we need to use a
        VSLDOI instruction.

        * config/rs6000/rs6000.h (EASY_VECTOR_MSB): Use mode mask to
        properly test for the MSB.

        * config/rs6000/altivec.md (VSLDOI splitter): Add splitter for
        vector constants that can be created with VSLDOI.

[gcc/testsuite]
2015-08-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

        PR target/67071
        * gcc.target/powerpc/pr67071-1.c: New file to test PR 67071 new
        vector constants.
        * gcc.target/powerpc/pr67071-2.c: Likewise.
        * gcc.target/powerpc/pr67071-3.c: Likewise.


Added:
    trunk/gcc/testsuite/gcc.target/powerpc/pr67071-1.c
    trunk/gcc/testsuite/gcc.target/powerpc/pr67071-2.c
    trunk/gcc/testsuite/gcc.target/powerpc/pr67071-3.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/rs6000/altivec.md
    trunk/gcc/config/rs6000/predicates.md
    trunk/gcc/config/rs6000/rs6000-protos.h
    trunk/gcc/config/rs6000/rs6000.c
    trunk/gcc/config/rs6000/rs6000.h
    trunk/gcc/testsuite/ChangeLog