From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 128106 invoked by alias); 30 Jul 2015 22:16:15 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 128080 invoked by uid 48); 30 Jul 2015 22:16:11 -0000 From: "meissner at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/67071] New: GCC misses an optimization to load vector constants Date: Thu, 30 Jul 2015 22:16:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 6.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: meissner at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone cf_gcchost cf_gcctarget cf_gccbuild Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-07/txt/msg02686.txt.bz2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67071 Bug ID: 67071 Summary: GCC misses an optimization to load vector constants Product: gcc Version: 6.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: meissner at gcc dot gnu.org Target Milestone: --- Host: powerpc64-unknown-linux-gnu Target: powerpc64-unknown-linux-gnu Build: powerpc64-unknown-linux-gnu Gcc has a logic error in rs6000.h which prevents it from being able to load vector constants with the most significant bit set. The code is: #define EASY_VECTOR_MSB(n,mode) \ (((unsigned HOST_WIDE_INT)n) == \ ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) However, if you look at the const_vector that is passed to easy_altivec_constant, the constant is sign extended, and EASY_VECTOR_MSB would not match. If we instead define EASY_VECTOR_MSG to do the mask before doing the comparison the test will succeed, and the code will generate the vector splat integer operation followed by vector shift left. #define EASY_VECTOR_MSB(n,mode) \ ((((unsigned HOST_WIDE_INT)n) & GET_MODE_MASK (mode)) == \ ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) A further optimization would be to recognize vector constants where the upper part can be formed via vector splat integer and then the bottom bits are all 0 or all 1, and we can use VSLDOI instruction with a secondary register that is all 0's or all 1's.