[Bug rtl-optimization/67124] [6 Regression] wrong code at -O1, -O2 and -O3 on x86_64-linux-gnu

["rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67124

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|target                      |rtl-optimization

--- Comment #12 from Richard Biener <rguenth at gcc dot gnu.org> ---
Hmm, indeed we fail to preserve the (subreg:DI (reg:TI xmm0)) in LRA

(insn 53 52 16 2 (set (reg:DI 21 xmm0 [orig:90 c ] [90])
        (mem/c:DI (plus:DI (reg/f:DI 7 sp)
                (const_int 8 [0x8])) [0 %sfp+-8 S8 A64])) t.c:16 85
{*movdi_internal}
     (nil))
...
(insn 17 16 49 2 (set (reg:V8HI 21 xmm0 [100])
        (vec_merge:V8HI (vec_duplicate:V8HI (reg:HI 0 ax [99]))
            (reg:V8HI 21 xmm0 [orig:90 c ] [90])
            (const_int 4 [0x4]))) t.c:16 3597 {sse2_pinsrw}
     (nil))

from

(insn 15 14 16 2 (parallel [
            (set (subreg:DI (reg/v:TI 90 [ c ]) 0)
                (ior:DI (reg:DI 97)
                    (reg:DI 95)))
            (clobber (reg:CC 17 flags))
        ]) t.c:16 398 {*iordi_1}
     (expr_list:REG_DEAD (reg:DI 97)
        (expr_list:REG_DEAD (reg:DI 95)
            (expr_list:REG_UNUSED (reg:CC 17 flags)
                (nil)))))
...
(insn 17 16 49 2 (set (reg:V8HI 100)
        (vec_merge:V8HI (vec_duplicate:V8HI (subreg:HI (reg:DI 99) 0))
            (subreg:V8HI (reg/v:TI 90 [ c ]) 0)
            (const_int 4 [0x4]))) t.c:16 3597 {sse2_pinsrw}

A plain DImode move to a DImode reg does not preserve the upper halves.  Not
sure if

(insn 53 52 16 2 (set (subreg:DI (reg:TI xmm0 0) [orig:90 c ] [90])
        (mem/c:DI (plus:DI (reg/f:DI 7 sp)
                (const_int 8 [0x8])) [0 %sfp+-8 S8 A64])) t.c:16 85
{*movdi_internal}
     (nil))

would be valid after "reload" though.

Maybe the bug is that we allocate a DImode register to a subreg of a TImode
destination at all.