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From: "olegendo at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/67126] New: [6 Regression][SH] gcc.target/sh/pr51244-12.c failures
Date: Wed, 05 Aug 2015 12:44:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67126

            Bug ID: 67126
           Summary: [6 Regression][SH] gcc.target/sh/pr51244-12.c failures
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: olegendo at gcc dot gnu.org
  Target Milestone: ---

There are two new failures:

FAIL: gcc.target/sh/pr51244-12.c scan-assembler-times negc 15
FAIL: gcc.target/sh/pr51244-12.c scan-assembler-times addc 3

which are triggered by the test case

int
test08 (char a)
{
  return ((a & 1) == 0) ? 0x7FFFFFFF : 0x80000000;
}

Before it compiled to:
        mov     r4,r0
        tst     #1,r0
        mov.l   .L69,r0
        rts     
        negc    r0,r0
.L70:
        .align 2
.L69:
        .long   -2147483648

now it compiles to:
        mov.l   .L69,r1
        shlr    r4
        mov     #0,r0
        rts     
        addc    r1,r0
.L70:
        .align 2
.L69:
        .long   2147483647

Using the tst insn in this case is a bit better.

Before combine would try this pattern

;; Use negc to store the T bit in a MSB of a reg in the following way:
;;      T = 0: 0x80000000 -> reg
;;      T = 1: 0x7FFFFFFF -> reg
;; This works because 0 - 0x80000000 = 0x80000000.
(define_insn_and_split "*mov_t_msb_neg"
  [(set (match_operand:SI 0 "arith_reg_dest")
        (minus:SI (const_int -2147483648)  ;; 0x80000000
                  (match_operand 1 "treg_set_expr")))
   (clobber (reg:SI T_REG))]

which now is matched as:

Successfully matched this instruction:
(parallel [
        (set (reg:SI 162 [ D.1897 ])
            (plus:SI (and:SI (reg:SI 4 r4 [ a+-3 ])
                    (const_int 1 [0x1]))
                (const_int 2147483647 [0x7fffffff])))
        (clobber (reg:SI 147 t))
    ])

This is the other *mov_t_msb_neg pattern variant.  The treg_set_expr is the
shlr insn in this case, which is non-negating and hence addc is used instead of
negc.  The (and (reg (const_int 1))) pattern above could be added as a special
case which would split into tst insn.