[Bug inline-asm/67317] New: [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[Bug inline-asm/67317] New: [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[myriachan at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

            Bug ID: 67317
           Summary: [x86] Silly code generation for
                    _addcarry_u32/_addcarry_u64
           Product: gcc
           Version: 5.2.0
            Status: UNCONFIRMED
          Severity: minor
          Priority: P3
         Component: inline-asm
          Assignee: unassigned at gcc dot gnu.org
          Reporter: myriachan at gmail dot com
  Target Milestone: ---

x86 intrinsics _addcarry_u32 and _addcarry_u64 generate silly code.  For
example, the following function to get the result of a 64-bit addition (the XOR
is to the output clearer):

        u64 testcarry(u64 a, u64 b, u64 c, u64 d)
        {
                u64 result0, result1;
                _addcarry_u64(_addcarry_u64(0, a, c, &result0), b, d,
&result1);
                return result0 ^ result1;
        }

This is the code generated with -O1, -O2 and -O3:

        xor     r8d, r8d
        add     r8b, -1
        adc     rdx, rdi
        setc    r8b
        mov     rax, rdx
        add     r8b, -1
        adc     rcx, rsi
        xor     rax, rcx
        ret

The first sillyness is that _addcarry_u64 does not optimize a compile-time
constant 0 being the first carry parameter.  Instead of "adc", it should just
use "add".

The second sillyness is with the use of r8b to store the carry flag, then using
"add r8b, -1" to put the result back into carry.

Instead, the code should be something like this:

        add     rdx, rdi
        mov     rax, rdx
        adc     rcx, rsi
        xor     rax, rcx
        ret

Naturally, for something this simple, I'd use unsigned __int128, but this came
up in large number math.

[Bug inline-asm/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Can you provide the full preprocessed source?

[Bug inline-asm/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |WAITING
   Last reconfirmed|                            |2015-08-25
     Ever confirmed|0                           |1

[Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[glisse at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

Marc Glisse <glisse at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |missed-optimization
             Target|                            |x86_64-*-*
             Status|WAITING                     |NEW
          Component|inline-asm                  |target

--- Comment #2 from Marc Glisse <glisse at gcc dot gnu.org> ---
Self-contained:

typedef unsigned long long u64;
u64 testcarry(u64 a, u64 b, u64 c, u64 d)
{
  u64 result0, result1;
  __builtin_ia32_addcarryx_u64(__builtin_ia32_addcarryx_u64(0, a, c, &result0),
b, d, &result1);
  return result0 ^ result1;
}

[Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

Segher Boessenkool <segher at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |segher at gcc dot gnu.org

--- Comment #3 from Segher Boessenkool <segher at gcc dot gnu.org> ---
These things would normally be taken care of by combine, but
combine of course does not know what the UNSPEC_ADD_CARRY's mean.
Does this need to be an unspec at all?

[Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

--- Comment #4 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Segher Boessenkool from comment #3)

> Does this need to be an unspec at all?

Of course not. We are looking to replace unspecs with standard RTXes. Do you
have any recommendation on how we can represent this carry-setting insn to
satisfy combine?
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Subject: [Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rguenth at gcc dot gnu.org,
                   |                            |ubizjak at gmail dot com

--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Uroš Bizjak from comment #2)
> (In reply to Allan Jensen from comment #0)
> 
> > Gcc will expand and detect field setting on 32-bit integers, but for some
> > reason miss the opportunity on 64-bit.
> 
> The immediates for 64bit logic insns are limited to sign-extended 32bit
> values, so this probably limits combine to combine several insns into one.

One example is:

(insn 8 6 9 2 (parallel [
            (set (reg:DI 100)
                (lshiftrt:DI (reg/v:DI 98 [ a ])
                    (const_int 48 [0x30])))
            (clobber (reg:CC 17 flags))
        ]) test.cpp:63 538 {*lshrdi3_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))
(insn 9 8 10 2 (parallel [
            (set (reg:DI 101)
                (ashift:DI (reg:DI 100)
                    (const_int 48 [0x30])))
            (clobber (reg:CC 17 flags))
        ]) test.cpp:63 504 {*ashldi3_1}
     (expr_list:REG_DEAD (reg:DI 100)
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (nil))))

combine tries to:

Trying 8 -> 9:
Failed to match this instruction:
(parallel [
        (set (reg:DI 101)
            (and:DI (reg/v:DI 98 [ a ])
                (const_int -281474976710656 [0xffff000000000000])))
        (clobber (reg:CC 17 flags))
    ])

However, tree optimizers pass to expand the following sequence:

  a = giveMe64 ();
  a$rgba_5 = MEM[(struct MyRgba64 *)&a];
  _6 = a$rgba_5 >> 16;
  _7 = a$rgba_5 >> 48;
  _8 = _7 << 48;
  _10 = _6 << 16;
  _11 = _10 & 4294967295;
  _13 = a$rgba_5 & 65535;
  _15 = _13 | 264913582817280;
  _16 = _8 | _15;
  _14 = _11 | _16;
  MEM[(struct MyRgba64 *)&D.2451] = _14;
  return D.2451;

Richi, can these shifts be converted to equivalent masking in tree optimizers?
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Subject: [Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #3)
> (In reply to Uroš Bizjak from comment #2)
> > (In reply to Allan Jensen from comment #0)
> > 
> > > Gcc will expand and detect field setting on 32-bit integers, but for some
> > > reason miss the opportunity on 64-bit.
> > 
> > The immediates for 64bit logic insns are limited to sign-extended 32bit
> > values, so this probably limits combine to combine several insns into one.
> 
> One example is:
> 
> (insn 8 6 9 2 (parallel [
>             (set (reg:DI 100)
>                 (lshiftrt:DI (reg/v:DI 98 [ a ])
>                     (const_int 48 [0x30])))
>             (clobber (reg:CC 17 flags))
>         ]) test.cpp:63 538 {*lshrdi3_1}
>      (expr_list:REG_UNUSED (reg:CC 17 flags)
>         (nil)))
> (insn 9 8 10 2 (parallel [
>             (set (reg:DI 101)
>                 (ashift:DI (reg:DI 100)
>                     (const_int 48 [0x30])))
>             (clobber (reg:CC 17 flags))
>         ]) test.cpp:63 504 {*ashldi3_1}
>      (expr_list:REG_DEAD (reg:DI 100)
>         (expr_list:REG_UNUSED (reg:CC 17 flags)
>             (nil))))
> 
> combine tries to:
> 
> Trying 8 -> 9:
> Failed to match this instruction:
> (parallel [
>         (set (reg:DI 101)
>             (and:DI (reg/v:DI 98 [ a ])
>                 (const_int -281474976710656 [0xffff000000000000])))
>         (clobber (reg:CC 17 flags))
>     ])
> 
> However, tree optimizers pass to expand the following sequence:
> 
>   a = giveMe64 ();
>   a$rgba_5 = MEM[(struct MyRgba64 *)&a];
>   _6 = a$rgba_5 >> 16;
>   _7 = a$rgba_5 >> 48;
>   _8 = _7 << 48;
>   _10 = _6 << 16;
>   _11 = _10 & 4294967295;
>   _13 = a$rgba_5 & 65535;
>   _15 = _13 | 264913582817280;
>   _16 = _8 | _15;
>   _14 = _11 | _16;
>   MEM[(struct MyRgba64 *)&D.2451] = _14;
>   return D.2451;
> 
> Richi, can these shifts be converted to equivalent masking in tree
> optimizers?


They should be or at least Naveen's patches should handle them.  There is an
open bug filed doing a >> N << N and one filed for a << N >> N already (I filed
it).
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Subject: [Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idg351

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Oh his patch only handled multiplies/divide and not shifts.  But it should be
easy to add them to match.pd to simplify this at the tree level.

[Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

--- Comment #5 from Segher Boessenkool <segher at gcc dot gnu.org> ---
Combine can handle most RTL expressions, although it sometimes
simplifies (or "simplifies") more than you want.

I think in this case what is already done in *add<mode>3_cc_overflow
will work well, but I do not know x86 CC modes terribly well.  You'll
need to experiment a bit to find something that works well in all
interesting cases.

[Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED
           Assignee|unassigned at gcc dot gnu.org      |ubizjak at gmail dot com

--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
Created attachment 36258
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36258&action=edit
Proposed patch

This patch changes expanders of carry-handling builtins to use
addqi3_cconly_overflow and canonicalizes carry hanling insn to what combine can
process:

(define_insn "addcarry<mode>"
  [(set (reg:CCC FLAGS_REG)
        (compare:CCC
          (plus:SWI48
            (plus:SWI48
              (match_operator:SWI48 4 "ix86_carry_flag_operator"
               [(match_operand 3 "flags_reg_operand") (const_int 0)])
              (match_operand:SWI48 1 "nonimmediate_operand" "%0"))
            (match_operand:SWI48 2 "nonimmediate_operand" "rm"))
          (match_dup 1)))
   (set (match_operand:SWI48 0 "register_operand" "=r")
        (plus:SWI48 (plus:SWI48 (match_op_dup 4
                                 [(match_dup 3) (const_int 0)])
                                (match_dup 1))
                    (match_dup 2)))]
  "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
  "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
  [(set_attr "type" "alu")
   (set_attr "use_carry" "1")
   (set_attr "pent_pair" "pu")
   (set_attr "mode" "<MODE>")])

and

(define_insn "subborrow<mode>"
  [(set (reg:CCC FLAGS_REG)
        (compare:CCC
          (match_operand:SWI48 1 "nonimmediate_operand" "0")
          (plus:SWI48
            (match_operator:SWI48 4 "ix86_carry_flag_operator"
             [(match_operand 3 "flags_reg_operand") (const_int 0)])
            (match_operand:SWI48 2 "nonimmediate_operand" "rm"))))
   (set (match_operand:SWI48 0 "register_operand" "=r")
        (minus:SWI48 (minus:SWI48 (match_dup 1)
                                  (match_op_dup 4
                                   [(match_dup 3) (const_int 0)]))
                     (match_dup 2)))]
  "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
  "sbb{<imodesuffix>}\t{%2, %0|%0, %2}"
  [(set_attr "type" "alu")
   (set_attr "use_carry" "1")
   (set_attr "pent_pair" "pu")
   (set_attr "mode" "<MODE>")])

The patch also rewrites expander to fix a bug, where carry-clobbering insns
were emitted inside carry-flag def-use chain.

For the testcase, patched gcc generates:

testcarry_u64:
        addq    %rdi, %rdx
        adcq    %rsi, %rcx
        movq    %rdx, %rax
        xorq    %rcx, %rax
        ret
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Subject: [Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|x86_64-*-*                  |x86
                 CC|uros at gcc dot gnu.org            |
   Target Milestone|---                         |5.3
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idg357

--- Comment #3 from Roger Orr <rogero at howzatt dot demon.co.uk> ---
The following code block also gives an ODR violation with the same versions of
gcc; in this case only a *single* translation unit is involved.

$ cat test.cxx
#include <memory>

template<typename T>
class D : public T {
    using mfn_t = void (D::*)();
    std::tuple<mfn_t> data{&D::foo};
public:
    void foo() {
        std::get<0>(data);
    }
};

namespace {
    struct S {};
}

int main() {
    D<S> obj;
}

$ /opt/gcc-5.2.0/bin/g++ -flto -Wodr -std=c++11 test.cxx
test.cxx:5:32: warning: type 'struct mfn_t' violates one definition rule
[-Wodr]
     using mfn_t = void (D::*)();
                                ^
/opt/gcc-5.2.0/include/c++/5.2.0/tuple:764:21: note: a different type is
defined in another translation unit
       typedef _Head type;
                     ^
test.cxx:5:32: note: the first difference of corresponding definitions is field
'__pfn'
     using mfn_t = void (D::*)();
                                ^
test.cxx:5:32: note: a field of same name but different type is defined in
another translation unit
lto1: note: type mismatch in parameter 1
test.cxx:4:20: note: type 'struct D' defined in anonymous namespace can not
match type 'struct D'
 class D : public T {
                    ^
test.cxx:4:7: note: the incompatible type defined in anonymous namespace in
another translation unit
 class D : public T {
       ^

(Giving the anonymous namespace a name removes the warnings.)

[Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[uros at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

--- Comment #7 from uros at gcc dot gnu.org ---
Author: uros
Date: Thu Aug 27 18:29:37 2015
New Revision: 227271

URL: https://gcc.gnu.org/viewcvs?rev=227271&root=gcc&view=rev
Log:
        PR target/67317
        * config/i386/i386.md (*add<mode>3_cc): Remove insn pattern.
        (addqi3_cc): Ditto.
        (UNSPEC_ADD_CARRY): Remove.
        (addqi3_cconly_overflow): New expander.
        (*add<dwi>3_doubleword): Split to add<mode>3_cconly_overflow.
        Adjust for changed add<mode>3_carry.
        (*neg<dwi>2_doubleword): Adjust for changed add<mode>3_carry.
        (*sub<dwi>3_doubleword): Adjust for changed sub<mode>3_carry.
        (<plusminus_insn><mode>3_carry): Remove expander.
        (*<plusminus_insn><mode>3_carry): Split insn pattern to
        add<mode>3_carry and sub<mode>3_carry.
        (plusminus_carry_mnemonic): Remove code attribute.
        (add<mode>3_carry): Canonicalize insn pattern.
        (*addsi3_carry_zext): Ditto.
        (sub<mode>3_carry): Ditto.
        (*subsi3_carry_zext): Ditto.
        (adcx<mode>3): Remove insn pattern.
        (addcarry<mode>): New insn pattern.
        (subborrow<mode>): Ditto.
        * config/i386/i386.c (ix86_expand_strlensi_unroll_1): Use
        gen_addqi3_cconly_overflow instead of gen_addqi3_cc.
        (ix86_expand_builtin) <case IX86_BUILTIN_SBB32,
        case IX86_BUILTIN_SBB64, case IX86_BUILTIN_ADDCARRY32,
        case IX86_BUILTIN_ADDCARRY64>: Use CODE_FOR_subborrowsi,
        CODE_FOR_subborrowdi, CODE_FOR_addcarrysi and CODE_FOR_addcarrydi.
        Rewrite expander to not clobber carry flag chains.

testsuite/ChangeLog:

        PR target/67317
        * gcc.target/i386/pr67317-1.c: New test.
        * gcc.target/i386/pr67317-2.c: Ditto.
        * gcc.target/i386/pr67317-3.c: Ditto.
        * gcc.target/i386/pr67317-4.c: Ditto.
        * gcc.target/i386/adx-addcarryx32-1.c: Also scan for adcl.
        * gcc.target/i386/adx-addcarryx32-2.c: Also scan for adcq.


Added:
    trunk/gcc/testsuite/gcc.target/i386/pr67317-1.c
    trunk/gcc/testsuite/gcc.target/i386/pr67317-2.c
    trunk/gcc/testsuite/gcc.target/i386/pr67317-3.c
    trunk/gcc/testsuite/gcc.target/i386/pr67317-4.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/i386.c
    trunk/gcc/config/i386/i386.md
    trunk/gcc/testsuite/ChangeLog
    trunk/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c
    trunk/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c

[Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[uros at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

--- Comment #8 from uros at gcc dot gnu.org ---
Author: uros
Date: Wed Sep  2 15:06:56 2015
New Revision: 227405

URL: https://gcc.gnu.org/viewcvs?rev=227405&root=gcc&view=rev
Log:
        Backport from mainline:
        2015-08-27  Uros Bizjak  <ubizjak@gmail.com>

        PR target/67317
        * config/i386/i386.md (*add<mode>3_cc): Remove insn pattern.
        (addqi3_cc): Ditto.
        (UNSPEC_ADD_CARRY): Remove.
        (addqi3_cconly_overflow): New expander.
        (*add<dwi>3_doubleword): Split to add<mode>3_cconly_overflow.
        Adjust for changed add<mode>3_carry.
        (*neg<dwi>2_doubleword): Adjust for changed add<mode>3_carry.
        (*sub<dwi>3_doubleword): Adjust for changed sub<mode>3_carry.
        (<plusminus_insn><mode>3_carry): Remove expander.
        (*<plusminus_insn><mode>3_carry): Split insn pattern to
        add<mode>3_carry and sub<mode>3_carry.
        (plusminus_carry_mnemonic): Remove code attribute.
        (add<mode>3_carry): Canonicalize insn pattern.
        (*addsi3_carry_zext): Ditto.
        (sub<mode>3_carry): Ditto.
        (*subsi3_carry_zext): Ditto.
        (adcx<mode>3): Remove insn pattern.
        (addcarry<mode>): New insn pattern.
        (subborrow<mode>): Ditto.
        * config/i386/i386.c (ix86_expand_strlensi_unroll_1): Use
        gen_addqi3_cconly_overflow instead of gen_addqi3_cc.
        (ix86_expand_builtin) <case IX86_BUILTIN_SBB32,
        case IX86_BUILTIN_SBB64, case IX86_BUILTIN_ADDCARRY32,
        case IX86_BUILTIN_ADDCARRY64>: Use CODE_FOR_subborrowsi,
        CODE_FOR_subborrowdi, CODE_FOR_addcarrysi and CODE_FOR_addcarrydi.
        Rewrite expander to not clobber carry flag chains.

testsuite/ChangeLog:

        Backport from mainline:
        2015-08-27  Uros Bizjak  <ubizjak@gmail.com>

        PR target/67317
        * gcc.target/i386/pr67317-1.c: New test.
        * gcc.target/i386/pr67317-2.c: Ditto.
        * gcc.target/i386/pr67317-3.c: Ditto.
        * gcc.target/i386/pr67317-4.c: Ditto.
        * gcc.target/i386/adx-addcarryx32-1.c: Also scan for adcl.
        * gcc.target/i386/adx-addcarryx32-2.c: Also scan for adcq.


Added:
    branches/gcc-5-branch/gcc/testsuite/gcc.target/i386/pr67317-1.c
    branches/gcc-5-branch/gcc/testsuite/gcc.target/i386/pr67317-2.c
    branches/gcc-5-branch/gcc/testsuite/gcc.target/i386/pr67317-3.c
    branches/gcc-5-branch/gcc/testsuite/gcc.target/i386/pr67317-4.c
Modified:
    branches/gcc-5-branch/gcc/ChangeLog
    branches/gcc-5-branch/gcc/config/i386/i386.c
    branches/gcc-5-branch/gcc/config/i386/i386.md
    branches/gcc-5-branch/gcc/testsuite/ChangeLog
    branches/gcc-5-branch/gcc/testsuite/gcc.target/i386/adx-addcarryx32-1.c
    branches/gcc-5-branch/gcc/testsuite/gcc.target/i386/adx-addcarryx64-1.c

[Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #9 from Uroš Bizjak <ubizjak at gmail dot com> ---
Fixed for 5.3+.
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idg414

--- Comment #4 from Janne Blomqvist <jb at gcc dot gnu.org> ---
Author: jb
Date: Wed Sep  2 15:13:35 2015
New Revision: 227406

URL: https://gcc.gnu.org/viewcvs?rev"7406&root=gcc&view=rev
Log:
PR 67414 Handle newlocale failure

2015-09-02  Janne Blomqvist  <jb@gcc.gnu.org>

        PR libfortran/67414
        * runtime/error.c (gf_strerror): Handle newlocale() failure.

Modified:
    branches/gcc-5-branch/libgfortran/ChangeLog
    branches/gcc-5-branch/libgfortran/runtime/error.c