[Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64

["ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67317

--- Comment #4 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Segher Boessenkool from comment #3)

> Does this need to be an unspec at all?

Of course not. We are looking to replace unspecs with standard RTXes. Do you
have any recommendation on how we can represent this carry-setting insn to
satisfy combine?
>From gcc-bugs-return-495631-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Tue Aug 25 17:33:31 2015
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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit
Date: Tue, 25 Aug 2015 17:33:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rguenth at gcc dot gnu.org,
                   |                            |ubizjak at gmail dot com

--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Uroš Bizjak from comment #2)
> (In reply to Allan Jensen from comment #0)
> 
> > Gcc will expand and detect field setting on 32-bit integers, but for some
> > reason miss the opportunity on 64-bit.
> 
> The immediates for 64bit logic insns are limited to sign-extended 32bit
> values, so this probably limits combine to combine several insns into one.

One example is:

(insn 8 6 9 2 (parallel [
            (set (reg:DI 100)
                (lshiftrt:DI (reg/v:DI 98 [ a ])
                    (const_int 48 [0x30])))
            (clobber (reg:CC 17 flags))
        ]) test.cpp:63 538 {*lshrdi3_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))
(insn 9 8 10 2 (parallel [
            (set (reg:DI 101)
                (ashift:DI (reg:DI 100)
                    (const_int 48 [0x30])))
            (clobber (reg:CC 17 flags))
        ]) test.cpp:63 504 {*ashldi3_1}
     (expr_list:REG_DEAD (reg:DI 100)
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (nil))))

combine tries to:

Trying 8 -> 9:
Failed to match this instruction:
(parallel [
        (set (reg:DI 101)
            (and:DI (reg/v:DI 98 [ a ])
                (const_int -281474976710656 [0xffff000000000000])))
        (clobber (reg:CC 17 flags))
    ])

However, tree optimizers pass to expand the following sequence:

  a = giveMe64 ();
  a$rgba_5 = MEM[(struct MyRgba64 *)&a];
  _6 = a$rgba_5 >> 16;
  _7 = a$rgba_5 >> 48;
  _8 = _7 << 48;
  _10 = _6 << 16;
  _11 = _10 & 4294967295;
  _13 = a$rgba_5 & 65535;
  _15 = _13 | 264913582817280;
  _16 = _8 | _15;
  _14 = _11 | _16;
  MEM[(struct MyRgba64 *)&D.2451] = _14;
  return D.2451;

Richi, can these shifts be converted to equivalent masking in tree optimizers?
>From gcc-bugs-return-495632-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Tue Aug 25 17:41:41 2015
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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Uroš Bizjak from comment #3)
> (In reply to Uroš Bizjak from comment #2)
> > (In reply to Allan Jensen from comment #0)
> > 
> > > Gcc will expand and detect field setting on 32-bit integers, but for some
> > > reason miss the opportunity on 64-bit.
> > 
> > The immediates for 64bit logic insns are limited to sign-extended 32bit
> > values, so this probably limits combine to combine several insns into one.
> 
> One example is:
> 
> (insn 8 6 9 2 (parallel [
>             (set (reg:DI 100)
>                 (lshiftrt:DI (reg/v:DI 98 [ a ])
>                     (const_int 48 [0x30])))
>             (clobber (reg:CC 17 flags))
>         ]) test.cpp:63 538 {*lshrdi3_1}
>      (expr_list:REG_UNUSED (reg:CC 17 flags)
>         (nil)))
> (insn 9 8 10 2 (parallel [
>             (set (reg:DI 101)
>                 (ashift:DI (reg:DI 100)
>                     (const_int 48 [0x30])))
>             (clobber (reg:CC 17 flags))
>         ]) test.cpp:63 504 {*ashldi3_1}
>      (expr_list:REG_DEAD (reg:DI 100)
>         (expr_list:REG_UNUSED (reg:CC 17 flags)
>             (nil))))
> 
> combine tries to:
> 
> Trying 8 -> 9:
> Failed to match this instruction:
> (parallel [
>         (set (reg:DI 101)
>             (and:DI (reg/v:DI 98 [ a ])
>                 (const_int -281474976710656 [0xffff000000000000])))
>         (clobber (reg:CC 17 flags))
>     ])
> 
> However, tree optimizers pass to expand the following sequence:
> 
>   a = giveMe64 ();
>   a$rgba_5 = MEM[(struct MyRgba64 *)&a];
>   _6 = a$rgba_5 >> 16;
>   _7 = a$rgba_5 >> 48;
>   _8 = _7 << 48;
>   _10 = _6 << 16;
>   _11 = _10 & 4294967295;
>   _13 = a$rgba_5 & 65535;
>   _15 = _13 | 264913582817280;
>   _16 = _8 | _15;
>   _14 = _11 | _16;
>   MEM[(struct MyRgba64 *)&D.2451] = _14;
>   return D.2451;
> 
> Richi, can these shifts be converted to equivalent masking in tree
> optimizers?


They should be or at least Naveen's patches should handle them.  There is an
open bug filed doing a >> N << N and one filed for a << N >> N already (I filed
it).
>From gcc-bugs-return-495633-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Tue Aug 25 18:03:25 2015
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Subject: [Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idg351

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Oh his patch only handled multiplies/divide and not shifts.  But it should be
easy to add them to match.pd to simplify this at the tree level.