From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 59433 invoked by alias); 25 Aug 2015 16:48:12 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 58935 invoked by uid 48); 25 Aug 2015 16:48:06 -0000 From: "ubizjak at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/67317] [x86] Silly code generation for _addcarry_u32/_addcarry_u64 Date: Tue, 25 Aug 2015 16:48:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 5.2.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: minor X-Bugzilla-Who: ubizjak at gmail dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-08/txt/msg01772.txt.bz2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D67317 --- Comment #4 from Uro=C5=A1 Bizjak --- (In reply to Segher Boessenkool from comment #3) > Does this need to be an unspec at all? Of course not. We are looking to replace unspecs with standard RTXes. Do you have any recommendation on how we can represent this carry-setting insn to satisfy combine? >>From gcc-bugs-return-495631-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Tue Aug 25 17:33:31 2015 Return-Path: Delivered-To: listarch-gcc-bugs@gcc.gnu.org Received: (qmail 9716 invoked by alias); 25 Aug 2015 17:33:31 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Delivered-To: mailing list gcc-bugs@gcc.gnu.org Received: (qmail 9672 invoked by uid 48); 25 Aug 2015 17:33:27 -0000 From: "ubizjak at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit Date: Tue, 25 Aug 2015 17:33:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 5.2.1 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: ubizjak at gmail dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-08/txt/msg01773.txt.bz2 Content-length: 2221 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D67351 Uro=C5=A1 Bizjak changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |rguenth at gcc dot gnu.org, | |ubizjak at gmail dot com --- Comment #3 from Uro=C5=A1 Bizjak --- (In reply to Uro=C5=A1 Bizjak from comment #2) > (In reply to Allan Jensen from comment #0) >=20 > > Gcc will expand and detect field setting on 32-bit integers, but for so= me > > reason miss the opportunity on 64-bit. >=20 > The immediates for 64bit logic insns are limited to sign-extended 32bit > values, so this probably limits combine to combine several insns into one. One example is: (insn 8 6 9 2 (parallel [ (set (reg:DI 100) (lshiftrt:DI (reg/v:DI 98 [ a ]) (const_int 48 [0x30]))) (clobber (reg:CC 17 flags)) ]) test.cpp:63 538 {*lshrdi3_1} (expr_list:REG_UNUSED (reg:CC 17 flags) (nil))) (insn 9 8 10 2 (parallel [ (set (reg:DI 101) (ashift:DI (reg:DI 100) (const_int 48 [0x30]))) (clobber (reg:CC 17 flags)) ]) test.cpp:63 504 {*ashldi3_1} (expr_list:REG_DEAD (reg:DI 100) (expr_list:REG_UNUSED (reg:CC 17 flags) (nil)))) combine tries to: Trying 8 -> 9: Failed to match this instruction: (parallel [ (set (reg:DI 101) (and:DI (reg/v:DI 98 [ a ]) (const_int -281474976710656 [0xffff000000000000]))) (clobber (reg:CC 17 flags)) ]) However, tree optimizers pass to expand the following sequence: a =3D giveMe64 (); a$rgba_5 =3D MEM[(struct MyRgba64 *)&a]; _6 =3D a$rgba_5 >> 16; _7 =3D a$rgba_5 >> 48; _8 =3D _7 << 48; _10 =3D _6 << 16; _11 =3D _10 & 4294967295; _13 =3D a$rgba_5 & 65535; _15 =3D _13 | 264913582817280; _16 =3D _8 | _15; _14 =3D _11 | _16; MEM[(struct MyRgba64 *)&D.2451] =3D _14; return D.2451; Richi, can these shifts be converted to equivalent masking in tree optimize= rs? >>From gcc-bugs-return-495632-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Tue Aug 25 17:41:41 2015 Return-Path: Delivered-To: listarch-gcc-bugs@gcc.gnu.org Received: (qmail 58479 invoked by alias); 25 Aug 2015 17:41:41 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Delivered-To: mailing list gcc-bugs@gcc.gnu.org Received: (qmail 58441 invoked by uid 48); 25 Aug 2015 17:41:37 -0000 From: "pinskia at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit Date: Tue, 25 Aug 2015 17:41:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 5.2.1 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: pinskia at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-08/txt/msg01774.txt.bz2 Content-length: 2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D67351 --- Comment #4 from Andrew Pinski --- (In reply to Uro=C5=A1 Bizjak from comment #3) > (In reply to Uro=C5=A1 Bizjak from comment #2) > > (In reply to Allan Jensen from comment #0) > >=20 > > > Gcc will expand and detect field setting on 32-bit integers, but for = some > > > reason miss the opportunity on 64-bit. > >=20 > > The immediates for 64bit logic insns are limited to sign-extended 32bit > > values, so this probably limits combine to combine several insns into o= ne. >=20 > One example is: >=20 > (insn 8 6 9 2 (parallel [ > (set (reg:DI 100) > (lshiftrt:DI (reg/v:DI 98 [ a ]) > (const_int 48 [0x30]))) > (clobber (reg:CC 17 flags)) > ]) test.cpp:63 538 {*lshrdi3_1} > (expr_list:REG_UNUSED (reg:CC 17 flags) > (nil))) > (insn 9 8 10 2 (parallel [ > (set (reg:DI 101) > (ashift:DI (reg:DI 100) > (const_int 48 [0x30]))) > (clobber (reg:CC 17 flags)) > ]) test.cpp:63 504 {*ashldi3_1} > (expr_list:REG_DEAD (reg:DI 100) > (expr_list:REG_UNUSED (reg:CC 17 flags) > (nil)))) >=20 > combine tries to: >=20 > Trying 8 -> 9: > Failed to match this instruction: > (parallel [ > (set (reg:DI 101) > (and:DI (reg/v:DI 98 [ a ]) > (const_int -281474976710656 [0xffff000000000000]))) > (clobber (reg:CC 17 flags)) > ]) >=20 > However, tree optimizers pass to expand the following sequence: >=20 > a =3D giveMe64 (); > a$rgba_5 =3D MEM[(struct MyRgba64 *)&a]; > _6 =3D a$rgba_5 >> 16; > _7 =3D a$rgba_5 >> 48; > _8 =3D _7 << 48; > _10 =3D _6 << 16; > _11 =3D _10 & 4294967295; > _13 =3D a$rgba_5 & 65535; > _15 =3D _13 | 264913582817280; > _16 =3D _8 | _15; > _14 =3D _11 | _16; > MEM[(struct MyRgba64 *)&D.2451] =3D _14; > return D.2451; >=20 > Richi, can these shifts be converted to equivalent masking in tree > optimizers? They should be or at least Naveen's patches should handle them. There is an open bug filed doing a >> N << N and one filed for a << N >> N already (I f= iled it). >>From gcc-bugs-return-495633-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Tue Aug 25 18:03:25 2015 Return-Path: Delivered-To: listarch-gcc-bugs@gcc.gnu.org Received: (qmail 7311 invoked by alias); 25 Aug 2015 18:03:25 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Delivered-To: mailing list gcc-bugs@gcc.gnu.org Received: (qmail 7216 invoked by uid 48); 25 Aug 2015 18:03:16 -0000 From: "pinskia at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit Date: Tue, 25 Aug 2015 18:03:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 5.2.1 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: pinskia at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-08/txt/msg01775.txt.bz2 Content-length: 263 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351 --- Comment #5 from Andrew Pinski --- Oh his patch only handled multiplies/divide and not shifts. But it should be easy to add them to match.pd to simplify this at the tree level.