[Bug middle-end/67351] New: Missed optimisation on 64-bit field compared to 32-bit

[Bug middle-end/67351] New: Missed optimisation on 64-bit field compared to 32-bit

[linux at carewolf dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

            Bug ID: 67351
           Summary: Missed optimisation on 64-bit field compared to 32-bit
           Product: gcc
           Version: 5.2.1
            Status: UNCONFIRMED
          Severity: enhancement
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: linux at carewolf dot com
  Target Milestone: ---

Created attachment 36253
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36253&action=edit
Test

Gcc will expand and detect field setting on 32-bit integers, but for some
reason miss the opportunity on 64-bit.

This was discovered as gcc was inexplicably slower compared to clang on the
64-bit case but not when using 32bit.

[Bug middle-end/67351] Missed optimisation on 64-bit field compared to 32-bit

[linux at carewolf dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

--- Comment #1 from Allan Jensen <linux at carewolf dot com> ---
Created attachment 36254
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36254&action=edit
Compiled test assembler

[Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

--- Comment #2 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Allan Jensen from comment #0)

> Gcc will expand and detect field setting on 32-bit integers, but for some
> reason miss the opportunity on 64-bit.

The immediates for 64bit logic insns are limited to sign-extended 32bit values,
so this probably limits combine to combine several insns into one.
>From gcc-bugs-return-495629-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Tue Aug 25 16:40:25 2015
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Subject: [Bug middle-end/64544] ../../gcc-svn/gcc/cgraphunit.c:2183:1: internal compiler error: in check_probability, at basic-block.h:581
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idd544

Marek Polacek <mpolacek at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #3 from Marek Polacek <mpolacek at gcc dot gnu.org> ---
Should be fixed.  If not, please reopen and be sure to add a preprocessed
source file.

[Bug target/67351] Missed optimisation on 64-bit field compared to 32-bit

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2015-08-26
     Ever confirmed|0                           |1

--- Comment #6 from Richard Biener <rguenth at gcc dot gnu.org> ---
Yes, << N >> N can be converted (but only for unsigned right shift or in VRP
with range information).  Convert the following fold-const.c code to match.pd:

      /* Transform (x >> c) << c into x & (-1<<c), or transform (x << c) >> c
         into x & ((unsigned)-1 >> c) for unsigned types.  */
      if (((code == LSHIFT_EXPR && TREE_CODE (arg0) == RSHIFT_EXPR)
           || (TYPE_UNSIGNED (type)
               && code == RSHIFT_EXPR && TREE_CODE (arg0) == LSHIFT_EXPR))
          && tree_fits_uhwi_p (arg1)
          && tree_to_uhwi (arg1) < prec
          && tree_fits_uhwi_p (TREE_OPERAND (arg0, 1))
          && tree_to_uhwi (TREE_OPERAND (arg0, 1)) < prec)
        { 
          HOST_WIDE_INT low0 = tree_to_uhwi (TREE_OPERAND (arg0, 1));
          HOST_WIDE_INT low1 = tree_to_uhwi (arg1);
          tree lshift;
          tree arg00;

          if (low0 == low1)
            { 
              arg00 = fold_convert_loc (loc, type, TREE_OPERAND (arg0, 0));

              lshift = build_minus_one_cst (type);
              lshift = const_binop (code, lshift, arg1);

              return fold_build2_loc (loc, BIT_AND_EXPR, type, arg00, lshift);
            }
        }

[Bug tree-optimization/67351] Missed optimisation on 64-bit field compared to 32-bit

[hs.naveen2u at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

--- Comment #8 from hs.naveen2u at gmail dot com ---
Patch that implements the optimization referred by Richard and Andrew.
https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00014.html

[Bug tree-optimization/67351] Missed optimisation on 64-bit field compared to 32-bit

[naveenh at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

--- Comment #9 from naveenh at gcc dot gnu.org ---
Author: naveenh
Date: Thu Sep  3 10:20:03 2015
New Revision: 227432

URL: https://gcc.gnu.org/viewcvs?rev=227432&root=gcc&view=rev
Log:
2015-09-03  Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>

        PR middle-end/67351

        gcc/ChangeLog: 
        * fold-const.c (fold_binary_loc) : Move 
        Transform (x >> c) << c into x & (-1<<c) or
        transform (x << c) >> c into x & ((unsigned)-1 >> c) for unsigned
        types using simplify and match.
        * match.pd (lshift (rshift @0 INTEGER_CST@1) @1) : New simplifier.
        (rshift (lshift @0 INTEGER_CST@1) @1) : New Simplifier.

        gcc/testsuite/ChangeLog: 
        * g++.dg/pr66752-2.C: New test.


Added:
    trunk/gcc/testsuite/g++.dg/pr67351.C
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/fold-const.c
    trunk/gcc/match.pd
    trunk/gcc/testsuite/ChangeLog

[Bug tree-optimization/67351] Missed optimisation on 64-bit field compared to 32-bit

[linux at carewolf dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

Allan Jensen <linux at carewolf dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #10 from Allan Jensen <linux at carewolf dot com> ---
With a recent gcc 6 this example appears perfectly optimized:
Disassembly of section .text:

0000000000000000 <_Z4testv>:
   0:   48 83 ec 08             sub    $0x8,%rsp
   4:   e8 00 00 00 00          callq  9 <_Z4testv+0x9>
   9:   25 ff ff 00 ff          and    $0xff00ffff,%eax
   e:   48 83 c4 08             add    $0x8,%rsp
  12:   0d 00 00 f0 00          or     $0xf00000,%eax
  17:   c3                      retq   
  18:   0f 1f 84 00 00 00 00    nopl   0x0(%rax,%rax,1)
  1f:   00 

0000000000000020 <_Z6test64v>:
  20:   48 83 ec 08             sub    $0x8,%rsp
  24:   e8 00 00 00 00          callq  29 <_Z6test64v+0x9>
  29:   48 ba ff ff ff ff 00    movabs $0xffff0000ffffffff,%rdx
  30:   00 ff ff 
  33:   48 83 c4 08             add    $0x8,%rsp
  37:   48 21 d0                and    %rdx,%rax
  3a:   48 ba 00 00 00 00 f0    movabs $0xf0f000000000,%rdx
  41:   f0 00 00 
  44:   48 09 d0                or     %rdx,%rax
  47:   c3                      retq

[Bug tree-optimization/67351] Missed optimisation on 64-bit field compared to 32-bit

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67351

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |6.0
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From: "bisqwit at iki dot fi" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug regression/67609] [Regression] Generates wrong code for SSE2 _mm_load_pd
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idg609

--- Comment #1 from Joel Yliluoma <bisqwit at iki dot fi> ---
For the record, changing _mm_load_pd(v) into _mm_set_pd(v[1],v[0]) will coax
GCC into generating correct code. The bug is related to _mm_load_pd().