[Bug target/67480] New: AVX512 bitwise logic operations pattern is incorrect

[Bug target/67480] New: AVX512 bitwise logic operations pattern is incorrect

[afomin.mailbox at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

            Bug ID: 67480
           Summary: AVX512 bitwise logic operations pattern is incorrect
           Product: gcc
           Version: 6.0
            Status: UNCONFIRMED
          Keywords: assemble-failure, wrong-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: afomin.mailbox at gmail dot com
                CC: kyukhin at gcc dot gnu.org, ubizjak at gmail dot com
  Target Milestone: ---
            Target: i?86-*-*, x86_64-*-*

For the loop in the attached testcase compiled with -mavx512bw -O2
-ftree-vectorize, we emit invalid AVX512 bitwise logic instruction. The reason
is wrong define_insn pattern: given a, let's say, bitwise `and` instruction
with Q/H mode and no masking for AVX512{F,BW} target, we may result in emitting
an vp<logic> instruction without <ssemodesufix> as there is no AVX512VL
support.

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

[afomin.mailbox at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

--- Comment #1 from Alexander Fomin <afomin.mailbox at gmail dot com> ---
Created attachment 36301
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36301&action=edit
Testcase

A reproducer

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

[afomin.mailbox at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

--- Comment #2 from Alexander Fomin <afomin.mailbox at gmail dot com> ---
Created attachment 36304
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36304&action=edit
Proposed fix

Proposed fix.
Splitting instruction pattern into two patterns, namely:
    (a) any logic instructions, S/D modes, masking is supported;
    (b) any logic instructions, Q/H modes, masking is not supported;
fixes the problem.

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

[afomin.mailbox at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

--- Comment #3 from Alexander Fomin <afomin.mailbox at gmail dot com> ---
There is another problem with the same pattern.
Suppose an V16SF insn mode and AVX512F target (e.g. KNL).
We'll emit something like vandps %zmm1, %zmm2, %zmm3; however, v<logic>ps
family requires AVX512VL and/or AVX512DQ CPUID.

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

[kyukhin at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

--- Comment #4 from Kirill Yukhin <kyukhin at gcc dot gnu.org> ---
Author: kyukhin
Date: Tue Sep 22 11:14:25 2015
New Revision: 228010

URL: https://gcc.gnu.org/viewcvs?rev=228010&root=gcc&view=rev
Log:
PR target/67480

gcc/
        * config/i386/sse.md (define_mode_iterator VI48_AVX_AVX512F): New.
        (define_mode_iterator VI12_AVX_AVX512F): New.
        (define_insn "<mask_codefor><code><mode>3<mask_name>"): Change
        all iterators to VI48_AVX_AVX512F. Extract remaining modes ...
        (define_insn "*<code><mode>3"): ... Into new pattern using
        VI12_AVX_AVX512F iterators without masking.

gcc/testsuite/
        * gcc.target/i386/pr67480.c: New test.

Added:
    trunk/gcc/testsuite/gcc.target/i386/pr67480.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/i386/sse.md
    trunk/gcc/testsuite/ChangeLog

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

[afomin.mailbox at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

Alexander Fomin <afomin.mailbox at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #5 from Alexander Fomin <afomin.mailbox at gmail dot com> ---
Please note that my previous comment is misleading: forced instruction mode
implies no masking at all.

[Bug target/67480] AVX512 bitwise logic operations pattern is incorrect

[kyukhin at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

--- Comment #6 from Kirill Yukhin <kyukhin at gcc dot gnu.org> ---
This bug is reproducible on gcc-5-branch