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From: "afomin.mailbox at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/67480] New: AVX512 bitwise logic operations pattern is incorrect
Date: Mon, 07 Sep 2015 13:57:00 -0000
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X-Bugzilla-Product: gcc
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X-Bugzilla-Version: 6.0
X-Bugzilla-Keywords: assemble-failure, wrong-code
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67480

            Bug ID: 67480
           Summary: AVX512 bitwise logic operations pattern is incorrect
           Product: gcc
           Version: 6.0
            Status: UNCONFIRMED
          Keywords: assemble-failure, wrong-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: afomin.mailbox at gmail dot com
                CC: kyukhin at gcc dot gnu.org, ubizjak at gmail dot com
  Target Milestone: ---
            Target: i?86-*-*, x86_64-*-*

For the loop in the attached testcase compiled with -mavx512bw -O2
-ftree-vectorize, we emit invalid AVX512 bitwise logic instruction. The reason
is wrong define_insn pattern: given a, let's say, bitwise `and` instruction
with Q/H mode and no masking for AVX512{F,BW} target, we may result in emitting
an vp<logic> instruction without <ssemodesufix> as there is no AVX512VL
support.