From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 119843 invoked by alias); 23 Oct 2015 08:30:03 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 119702 invoked by uid 48); 23 Oct 2015 08:29:58 -0000 From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/67609] [5/6 Regression] Generates wrong code for SSE2 _mm_load_pd Date: Fri, 23 Oct 2015 08:30:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 5.2.1 X-Bugzilla-Keywords: ra, wrong-code X-Bugzilla-Severity: major X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 5.3 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-10/txt/msg01920.txt.bz2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67609 --- Comment #26 from Richard Biener --- (In reply to Richard Henderson from comment #22) > (In reply to Jeffrey A. Law from comment #21) > > So going back to the original problem, for a subreg of a multi-word reg, > > why can't we simplify that down to a suitably sized reg? > > Because we're dealing with registers of different sizes. > > Assigning to a subreg as the low-part of a multi-word pseudo only > makes sense when talking about general registers, which is the only > place that "word_mode" applies. Hmm, I don't see this documented anywhere. In fact there is no such thing as a "vector register", there are only vector modes. And we are using %xmm for plain SF/DFmode all over the place. Note that in the particular case the mode we subreg is TImode, not a vector mode. > When talking about vector registers, which are universally larger > than word-mode, we cannot simply assign to a subreg. > > There is a vec_set named pattern that can perform an insertion into > a vector element, like what's being demonstrated in the test source > here. Ideally that's how we'd have expanded this originally. Indeed, if expand can see we are setting the low part of a vector then it should try using vec_set. Auditing of other targets might be necessary here though. And of course the i386 backend might end up choosing movdf for this operation anyway... > We already have ix86_cannot_change_mode_class to avoid the cases > that we knew we couldn't support, e.g. QI and HImode loads/stores. > But perhaps we should prevent all size-changing mode changes for > the vector registers. That may be a workaround for x86 but I don't see how this fixes the issue in general given that targets may have general registers larger than word_mode (is x32 TARGET_64BIT?).