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From: "afomin.mailbox at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/67849] New: AVX512 Hitting upper-bank register on extract insn split
Date: Mon, 05 Oct 2015 11:14:00 -0000 [thread overview]
Message-ID: <bug-67849-4@http.gcc.gnu.org/bugzilla/> (raw)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67849
Bug ID: 67849
Summary: AVX512 Hitting upper-bank register on extract insn
split
Product: gcc
Version: 6.0
Status: UNCONFIRMED
Keywords: assemble-failure, wrong-code
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: afomin.mailbox at gmail dot com
CC: kyukhin at gcc dot gnu.org
Target Milestone: ---
Target: i?86-*-*, x86_64-*-*
This issue has been found while compiling SPEC2006 CPU 447.dealII benchmark for
KNL architecture.
Given a machine that does not have AVX512VL extension, following "else" branch
for vec_extract_lo insn described below ...
(define_insn "vec_extract_lo_<mode><mask_name>"
[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
"=<store_mask_constraint>,v")
(vec_select:<ssehalfvecmode>
(match_operand:V8FI 1 "nonimmediate_operand" "v,m")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
"TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
if (<mask_applied>)
return "vextract<shuffletype>64x4\t{$0x0, %1,
%0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
else
return "#";
}
;; ...
)
... may result in a split using YMMs from upper bank, hence emitting invalid
insn like
vextractf128 $0x1, %ymm31, %xmm0
We should tune insn constraints to avoid this issue.
next reply other threads:[~2015-10-05 11:14 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-05 11:14 afomin.mailbox at gmail dot com [this message]
2015-10-06 13:50 ` [Bug target/67849] " kyukhin at gcc dot gnu.org
2015-10-06 14:15 ` afomin.mailbox at gmail dot com
2015-10-12 11:04 ` kyukhin at gcc dot gnu.org
2015-10-12 11:16 ` afomin.mailbox at gmail dot com
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