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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug c/67967] [5.2/6 Regression] ICE in i386_pe_seh_unwind_emit
Date: Wed, 14 Oct 2015 20:19:00 -0000	[thread overview]
Message-ID: <bug-67967-4-jskfx5GMVk@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-67967-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67967

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2015-10-14
           Assignee|unassigned at gcc dot gnu.org      |ubizjak at gmail dot com
     Ever confirmed|0                           |1

--- Comment #5 from Uroš Bizjak <ubizjak at gmail dot com> ---
Created attachment 36513
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36513&action=edit
Alternative patch that avoids REG_CFA_EXPRESSION for aligned moves

I'm testing the above patch.
>From gcc-bugs-return-499573-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Wed Oct 14 20:46:29 2015
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From: "vogt at linux dot vnet.ibm.com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/67443] [5/6 regression] DSE removes required store instruction
Date: Wed, 14 Oct 2015 20:46:00 -0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?idg443

--- Comment #7 from Dominik Vogt <vogt at linux dot vnet.ibm.com> ---
Almost.  Note the strange bit numbering on s390.  The highest order bit in any
operation always has the number 0, and the lowest order bit has the highest
number.  So the 8-bit-move instruction "mvi" stores a byte into *a (bit 0-7),
then the 32-bit-and instruction "n" reads *a as a 32 bit value.  The bits 0-7
are the highest order bits of the result, so the value read is actually
0x03xxxxxx (bits 0-7 have the value 0x03, the rest is random data).

(Actually, I couldn't read this assembly code right without the help of a
debugger.)

                       # r2 contains the address a at start of function
  larl  %r5,.L3
  mvi  0(%r2),3        # b-byte store of value 3 to the *(a + 0)
                       #   -> memory at a: 03 ** ** ** ** ** ** **
  l  %r1,.L4-.L3(%r5)  # 32-bit-load 0xff000000 to r1

  n  %r1,0(%r2)        # 32-bit "and" of *(a + 0) and $1, result
                       # stored in r1 -> 0x03000000

  oill  %r1,5          # 64-bit "or" of r1 with the immediate value
                       # 0x00000000 00000005
                       # r1 -> 0x03000005
  st  %r1,0(%r2)       # 32-bit store or r1 to a
                       #   -> memory at a: 03 00 00 05 ** ** ** **
  br  %r14
.L3:
.L4:
  .long  -16777216


  parent reply	other threads:[~2015-10-14 20:19 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-14 17:14 [Bug c/67967] New: " tprince at computer dot org
2015-10-14 17:15 ` [Bug c/67967] " tprince at computer dot org
2015-10-14 17:19 ` tprince at computer dot org
2015-10-14 18:49 ` ubizjak at gmail dot com
2015-10-14 18:52 ` [Bug c/67967] [5.2/6 Regression] " tkoenig at gcc dot gnu.org
2015-10-14 18:55 ` ubizjak at gmail dot com
2015-10-14 20:19 ` ubizjak at gmail dot com [this message]
2015-10-14 21:18 ` uros at gcc dot gnu.org
2015-10-14 22:30 ` uros at gcc dot gnu.org
2015-10-15  9:44 ` [Bug target/67967] " rguenth at gcc dot gnu.org

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