From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 74711 invoked by alias); 14 Oct 2015 20:19:27 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Received: (qmail 74647 invoked by uid 48); 14 Oct 2015 20:19:23 -0000 From: "ubizjak at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug c/67967] [5.2/6 Regression] ICE in i386_pe_seh_unwind_emit Date: Wed, 14 Oct 2015 20:19:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: c X-Bugzilla-Version: 6.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: major X-Bugzilla-Who: ubizjak at gmail dot com X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: ubizjak at gmail dot com X-Bugzilla-Target-Milestone: 5.3 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_status cf_reconfirmed_on assigned_to everconfirmed attachments.created Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-10/txt/msg01127.txt.bz2 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D67967 Uro=C5=A1 Bizjak changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |ASSIGNED Last reconfirmed| |2015-10-14 Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail do= t com Ever confirmed|0 |1 --- Comment #5 from Uro=C5=A1 Bizjak --- Created attachment 36513 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=3D36513&action=3Dedit Alternative patch that avoids REG_CFA_EXPRESSION for aligned moves I'm testing the above patch. >>From gcc-bugs-return-499573-listarch-gcc-bugs=gcc.gnu.org@gcc.gnu.org Wed Oct 14 20:46:29 2015 Return-Path: Delivered-To: listarch-gcc-bugs@gcc.gnu.org Received: (qmail 98760 invoked by alias); 14 Oct 2015 20:46:29 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org Delivered-To: mailing list gcc-bugs@gcc.gnu.org Received: (qmail 98725 invoked by uid 48); 14 Oct 2015 20:46:25 -0000 From: "vogt at linux dot vnet.ibm.com" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/67443] [5/6 regression] DSE removes required store instruction Date: Wed, 14 Oct 2015 20:46:00 -0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 5.2.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: vogt at linux dot vnet.ibm.com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 5.3 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-SW-Source: 2015-10/txt/msg01128.txt.bz2 Content-length: 1378 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67443 --- Comment #7 from Dominik Vogt --- Almost. Note the strange bit numbering on s390. The highest order bit in any operation always has the number 0, and the lowest order bit has the highest number. So the 8-bit-move instruction "mvi" stores a byte into *a (bit 0-7), then the 32-bit-and instruction "n" reads *a as a 32 bit value. The bits 0-7 are the highest order bits of the result, so the value read is actually 0x03xxxxxx (bits 0-7 have the value 0x03, the rest is random data). (Actually, I couldn't read this assembly code right without the help of a debugger.) # r2 contains the address a at start of function larl %r5,.L3 mvi 0(%r2),3 # b-byte store of value 3 to the *(a + 0) # -> memory at a: 03 ** ** ** ** ** ** ** l %r1,.L4-.L3(%r5) # 32-bit-load 0xff000000 to r1 n %r1,0(%r2) # 32-bit "and" of *(a + 0) and $1, result # stored in r1 -> 0x03000000 oill %r1,5 # 64-bit "or" of r1 with the immediate value # 0x00000000 00000005 # r1 -> 0x03000005 st %r1,0(%r2) # 32-bit store or r1 to a # -> memory at a: 03 00 00 05 ** ** ** ** br %r14 .L3: .L4: .long -16777216