[Bug target/68102] New: [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64

[Bug target/68102] New: [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68102

            Bug ID: 68102
           Summary: [5/6 Regression] ICE: RTL check: expected code 'reg',
                    have 'subreg' in rhs_regno, at rtl.h:1782 with
                    float64x1_t @ aarch64
           Product: gcc
           Version: 6.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---

Created attachment 36591
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=36591&action=edit
reduced testcase

This might be a fallback of PR60825.

The code ICEs with:
typedef __Float64x1_t float64x1_t;
but works with:
typedef double float64x1_t;
which was the case for 4.x

The code has #include "arm_neon.h", but it can be changed to the typedef above.

RTL checking is needed to get this ICE.

Compiler output:
$ gcc -O2 testcase.c
testcase.c: In function 'foo':
testcase.c:20:1: internal compiler error: RTL check: expected code 'reg', have
'subreg' in rhs_regno, at rtl.h:1782
 }
 ^
0xa90e27 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
char const*)
        /mnt/svn/gcc-trunk/gcc/rtl.c:811
0x55f883 rhs_regno
        /mnt/svn/gcc-trunk/gcc/rtl.h:1782
0x10571a6 rhs_regno
        /mnt/svn/gcc-trunk/gcc/config/aarch64/atomics.md:510
0x10571a6 split_insns(rtx_def*, rtx_insn*)
        /mnt/svn/gcc-trunk/gcc/config/aarch64/aarch64.md:1031
0x7a17b0 try_split(rtx_def*, rtx_insn*, int)
        /mnt/svn/gcc-trunk/gcc/emit-rtl.c:3666
0xa4a030 split_insn
        /mnt/svn/gcc-trunk/gcc/recog.c:2874
0xa5249f split_all_insns()
        /mnt/svn/gcc-trunk/gcc/recog.c:2964
0xa52588 execute
        /mnt/svn/gcc-trunk/gcc/recog.c:3881
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <http://gcc.gnu.org/bugs.html> for instructions.

Tested revisions:
r229293 - ICE
5-branch r229292 - ICE (even at -O1)
4_9-branch r229291 - OK (it is using the other typedef)

[Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68102

Zdenek Sojka <zsojka at seznam dot cz> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |ice-on-valid-code
             Target|                            |aarch64-unknown-linux-gnu
      Known to work|                            |4.9.4
               Host|                            |x86_64-pc-linux-gnu
      Known to fail|                            |5.2.1, 6.0

--- Comment #1 from Zdenek Sojka <zsojka at seznam dot cz> ---
Forgot version:

$ xgcc -v
Using built-in specs.
COLLECT_GCC=/home/smatz/build-trunk-229293-lto-fortran-checking-yes-rtl-df-disable-bootstrap-disable-graphite-aarch64/gcc/xgcc
Target: aarch64-unknown-linux-gnu
Configured with: /mnt/svn/gcc-trunk//configure --disable-bootstrap
--enable-checking=yes,rtl,df --enable-languages=c,c++
--prefix=/mnt/svn/gcc-trunk//binary-229293-lto-fortran-checking-yes-rtl-df-disable-bootstrap-disable-graphite-aarch64/
--without-cloog --without-ppl --without-isl --host=x86_64-pc-linux-gnu
--target=aarch64-unknown-linux-gnu --build=x86_64-pc-linux-gnu
--with-sysroot=/home/aarch64-chroot
--with-as=/usr/libexec/gcc/aarch64-unknown-linux-gnu/as
--with-ld=/usr/libexec/gcc/aarch64-unknown-linux-gnu/ld
Thread model: posix
gcc version 6.0.0 20151025 (experimental) (GCC)

[Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68102

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |5.3

[Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68102

ktkachov at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2015-10-27
                 CC|                            |ktkachov at gcc dot gnu.org
           Assignee|unassigned at gcc dot gnu.org      |ktkachov at gcc dot gnu.org
     Ever confirmed|0                           |1

--- Comment #2 from ktkachov at gcc dot gnu.org ---
Confirmed.
This needs RTL checking enabled to trigger

[Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68102

--- Comment #3 from ktkachov at gcc dot gnu.org ---
Author: ktkachov
Date: Tue Oct 27 18:32:37 2015
New Revision: 229455

URL: https://gcc.gnu.org/viewcvs?rev=229455&root=gcc&view=rev
Log:
[AArch64] PR 68102: Check that operand is REG before checking the REGNO in
mov-immediate splitters

        PR target/68102
        * config/aarch64/aarch64.md (*movsi_aarch64): Check that
        operands[0] is a reg before taking its REGNO in split condition.
        (*movdi_aarch64): Likewise.

        * gcc.target/aarch64/pr68102_1.c: New test.


Added:
    trunk/gcc/testsuite/gcc.target/aarch64/pr68102_1.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/aarch64/aarch64.md
    trunk/gcc/testsuite/ChangeLog

[Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68102

--- Comment #4 from ktkachov at gcc dot gnu.org ---
Author: ktkachov
Date: Wed Oct 28 13:32:17 2015
New Revision: 229483

URL: https://gcc.gnu.org/viewcvs?rev=229483&root=gcc&view=rev
Log:
[AArch64] PR 68102: Check that operand is REG before checking the REGNO in
mov-immediate splitters

        Backport from mainline
        2015-10-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

        PR target/68102
        * config/aarch64/aarch64.md (*movsi_aarch64): Check that
        operands[0] is a reg before taking its REGNO in split condition.
        (*movdi_aarch64): Likewise.

        * gcc.target/aarch64/pr68102_1.c: New test.


Added:
    branches/gcc-5-branch/gcc/testsuite/gcc.target/aarch64/pr68102_1.c
Modified:
    branches/gcc-5-branch/gcc/ChangeLog
    branches/gcc-5-branch/gcc/config/aarch64/aarch64.md
    branches/gcc-5-branch/gcc/testsuite/ChangeLog

[Bug target/68102] [5/6 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1782 with float64x1_t @ aarch64

[ktkachov at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68102

ktkachov at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #5 from ktkachov at gcc dot gnu.org ---
Fixed on trunk and GCC 5