From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 4B1723858CDA; Sun, 16 Jul 2023 17:15:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4B1723858CDA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1689527710; bh=PiMJyCql8SRfHiCABDHitsCWRGvOOZeC6nRtemBJRgs=; h=From:To:Subject:Date:In-Reply-To:References:From; b=o5IfyaoD9VLKpu8kiCh0uTZvBkCLeXVfkPkf79VM9rGalCm2e2iXdan7tHMwRiO6v fkeIxTMHbqDYMBJwhLLMB2/1GAInlpg6ocXUq31t0a903s1UrSxxpKsLdBKY7ourug RnJqMfdq62sog/P4u1v1CDr35tKnoPV83o1UQR9k= From: "pinskia at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug middle-end/68360] GCC bitfield processing code is very inefficient Date: Sun, 16 Jul 2023 17:15:10 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: middle-end X-Bugzilla-Version: 5.2.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: pinskia at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: pinskia at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: see_also Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D68360 Andrew Pinski changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://gcc.gnu.org/bugzill | |a/show_bug.cgi?id=3D107601 --- Comment #8 from Andrew Pinski --- (In reply to Thomas Koenig from comment #7) > Using an indexed load byte/store byte would be an advantage for foo, at > least. That would be more related to PR 107601 and less to do with this issue. Sin= ce for riscv SLOW_BYTE_ACCESS is set, then all bitfields accesses are widen. B= ut then you want to have them widen normally; otherwise you get other bad code generation ... Note riscv with zbs in the testcase in comment #7 will be one bseti: ld a5,0(a0) bseti a5,a5,42 sd a5,0(a0) So it is less of an issue ...=