From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 86C91386F0C7; Mon, 27 Jun 2022 06:49:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 86C91386F0C7 From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/7061] Access of bytes in struct parameters Date: Mon, 27 Jun 2022 06:49:24 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 3.2 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Jun 2022 06:49:24 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D7061 --- Comment #11 from CVS Commits --- The master branch has been updated by Roger Sayle : https://gcc.gnu.org/g:64d4f27a0ce47e97867512bda7fa5683acf8a134 commit r13-1282-g64d4f27a0ce47e97867512bda7fa5683acf8a134 Author: Roger Sayle Date: Mon Jun 27 07:47:40 2022 +0100 Implement __imag__ of float _Complex using shufps on x86_64. This patch is a follow-up improvement to my recent patch for PR rtl-optimization/7061. That patch added the test case gcc.target/i386/pr7061-2.c: float im(float _Complex a) { return __imag__ a; } For which GCC on x86_64 currently generates: movq %xmm0, %rax shrq $32, %rax movd %eax, %xmm0 ret but with this patch we now generate (the same as LLVM): shufps $85, %xmm0, %xmm0 ret This is achieved by providing a define_insn_and_split that allows truncated lshiftrt:DI by 32 to be performed on either SSE or general regs, where if the register allocator prefers to use SSE, we split to a shufps_v4si, or if not, we use a regular shrq. 2022-06-27 Roger Sayle gcc/ChangeLog PR rtl-optimization/7061 * config/i386/i386.md (*highpartdisi2): New define_insn_and_spl= it. gcc/testsuite/ChangeLog PR rtl-optimization/7061 * gcc.target/i386/pr7061-2.c: Update to look for shufps.=