[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #17 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Created attachment 49162
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49162&action=edit
Full Neon intrinsics list as of 2020-09-01.

Full Neon intrinsics list as of 2020-09-01.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #18 from Christophe Lyon <clyon at gcc dot gnu.org> ---
The list at
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics
has a new format (the list is split in 146 pages, I couldn't find how to get
the list on a single page). So I used 'lynx' to download all the pages in a
text format, which I am attaching now.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #19 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Created attachment 49165
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49165&action=edit
Full list of intrinsics documented for v7/a32/a64

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #20 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Created attachment 49166
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49166&action=edit
Full list of intrinsics documented for a32/a64

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #21 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Created attachment 49167
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49167&action=edit
Full list of intrinsics documented for a64

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #22 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Applying the recipe from comment #6, the current list of duplicates is:
New ones:
      2 vcmla_laneq_f16
      2 vcmla_rot180_laneq_f16
      2 vcmla_rot270_laneq_f16
      2 vcmla_rot90_laneq_f16

Known, expected (see comment #15):
      2 vshll_high_n_s16
      2 vshll_high_n_s32
      2 vshll_high_n_s8
      2 vshll_high_n_u16
      2 vshll_high_n_u32
      2 vshll_high_n_u8
      2 vshll_n_s16
      2 vshll_n_s32
      2 vshll_n_s8
      2 vshll_n_u16
      2 vshll_n_u32
      2 vshll_n_u8

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #23 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Created attachment 49168
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49168&action=edit
v7 intrinsics not supported by the aarch64 target

Update 2020-09-01

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #24 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Created attachment 49169
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49169&action=edit
a32/a64 intrinsics not supported by the aarch64 target

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #25 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Created attachment 49170
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49170&action=edit
a64 intrinsics not supported by the aarch64 target

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #26 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Created attachment 49171
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49171&action=edit
v7 intrinsics not supported by the aarch32/arm target

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #27 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Created attachment 49172
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=49172&action=edit
a32/a64 intrinsics not supported by the aarch32/arm target

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[sripar01 at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

SRINATH PARVATHANENI <sripar01 at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |sripar01 at gcc dot gnu.org

--- Comment #28 from SRINATH PARVATHANENI <sripar01 at gcc dot gnu.org> ---
(In reply to Christophe Lyon from comment #24)
> Created attachment 49169 [details]
> a32/a64 intrinsics not supported by the aarch64 target

The __crc* intrinsic are already supported (but defined in arm_acle.h instead).
arm_acle.h:__crc32b (uint32_t __a, uint8_t __b)
arm_acle.h:__crc32cb (uint32_t __a, uint8_t __b)
arm_acle.h:__crc32cd (uint32_t __a, uint64_t __b)
arm_acle.h:__crc32ch (uint32_t __a, uint16_t __b)
arm_acle.h:__crc32cw (uint32_t __a, uint32_t __b)
arm_acle.h:__crc32d (uint32_t __a, uint64_t __b)
arm_acle.h:__crc32h (uint32_t __a, uint16_t __b)
arm_acle.h:__crc32w (uint32_t __a, uint32_t __b)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #29 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:fa9ad35dae03dcb20c4ccb50ba1b351a8ab77970

commit r11-3352-gfa9ad35dae03dcb20c4ccb50ba1b351a8ab77970
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 11:58:36 2020 +0100

    AArch64: Implement poly-type vadd intrinsics

    This implements the vadd[p]_p* intrinsics.
    In terms of functionality they are aliases of veor operations on the
relevant unsigned types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vadd_p8, vadd_p16, vadd_p64, vaddq_p8,
            vaddq_p16, vaddq_p64, vaddq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vadd_poly_1.c: New test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #30 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:d4703be185b422f637deebd3bb9222a41c8023d6

commit r11-3353-gd4703be185b422f637deebd3bb9222a41c8023d6
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:00:38 2020 +0100

    AArch64: Implement missing vceq*_p* intrinsics

    This patch implements some missing vceq* intrinsics on poly types.
    The behaviour is to produce the appropriate CMEQ instruction as for the
unsigned types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vceqq_p64, vceqz_p64, vceqzq_p64):
Define.

    gcc/testsuite/

            PR target/71233
            * gcc.target/aarch64/simd/vceq_poly_1.c: New test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #31 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:30957092db46d8798e632feefb5df634488dbb33

commit r11-3354-g30957092db46d8798e632feefb5df634488dbb33
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:03:49 2020 +0100

    AArch64: Implement missing vcls intrinsics on unsigned types

    This patch implements some missing intrinsics that perform a CLS on
unsigned SIMD types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vcls_u8, vcls_u16, vcls_u32,
            vclsq_u8, vclsq_u16, vclsq_u32): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vcls_unsigned_1.c: New test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #32 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:874bdcd54b53283a82418649ea7457c1d6804562

commit r8-10526-g874bdcd54b53283a82418649ea7457c1d6804562
Author: Vlad Lazar <vlad.lazar@arm.com>
Date:   Fri Aug 31 15:00:54 2018 +0000

    [AArch64] Implement new intrinsics vabsd_s64 and vnegd_s64.

    gcc/
    2018-08-31  Vlad Lazar  <vlad.lazar@arm.com>

            PR target/71233
            * config/aarch64/arm_neon.h (vabsd_s64): New.
            (vnegd_s64): Likewise.

    gcc/testsuite/
    2018-08-31  Vlad Lazar  <vlad.lazar@arm.com>

            PR target/71233
            * gcc.target/aarch64/scalar_intrinsics.c (test_vnegd_s64): New.
            * gcc.target/aarch64/vneg_s.c (RUN_TEST_SCALAR): New.
            (test_vnegd_s64): Likewise.
            * gcc.target/aarch64/vnegd_s64.c: New.
            * gcc.target/aarch64/vabsd_s64.c: New.

    (cherry picked from commit 66da5b53107962a1c115a9686f2220de27f276f7)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #33 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:d23ea1e865301cd45f14ccbdb0bca49251fde9e1

commit r11-3388-gd23ea1e865301cd45f14ccbdb0bca49251fde9e1
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 10:29:17 2020 +0100

    AArch64: Implement vstrq_p128 intrinsic

    This patch implements the missing vstrq_p128 intrinsic.
    It just performs a store of the poly128_t argument to a memory location.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vstrq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vstrq_p128_1.c: New test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #34 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:f2868e4bcff2c7b882d01231f039459c00e59d7b

commit r11-3389-gf2868e4bcff2c7b882d01231f039459c00e59d7b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 10:32:42 2020 +0100

    AArch64: Implement vldrq_p128 intrinsic

    This patch implements the missing vldrq_p128 intrinsic that just loads from
the appropriate pointer.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vldrq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vldrq_p128_1.c: New test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #35 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:e8e818399d70c5a5a3d30a54d305c6e2b92e2c66

commit r11-3390-ge8e818399d70c5a5a3d30a54d305c6e2b92e2c66
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 11:07:50 2020 +0100

    AArch64: Implement missing _p64 intrinsics for vector permutes

    This patch implements some missing vector permute intrinsics operating on
poly64x2_t types.
    They are implemented identically to their uint64x2_t brethren.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vtrn1q_p64, vtrn2q_p64, vuzp1q_p64,
            vuzp2q_p64, vzip1q_p64, vzip2q_p64): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/trn_zip_p64_1.c: New test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #36 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:02b5377b3766804059b7824330d33d0e1cef2e5b

commit r11-3392-g02b5377b3766804059b7824330d33d0e1cef2e5b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 12:02:29 2020 +0100

    AArch64: Implement missing vrndns_f32 intrinsic

    This patch implements the missing vrndns_f32 intrinsic. This operates on a
scalar float32_t value.
    It can be mapped down to a __builtin_aarch64_frintnsf builtin.

    This patch does that.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/aarch64-simd-builtins.def (frintn): Use
BUILTIN_VHSDF_HSDF
            for modes.  Remove explicit hf instantiation.
            * config/aarch64/arm_neon.h (vrndns_f32): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vrndns_f32_1.c: New test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #37 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:65c9878641cbe0ed898aa7047b7b994e9d4a5bb1

commit r11-3402-g65c9878641cbe0ed898aa7047b7b994e9d4a5bb1
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 17:37:58 2020 +0100

    AArch64: Implement missing p128<->f64 reinterpret intrinsics

    This patch implements the missing reinterprets to and from poly128_t and
    float64x2_t.
    I've plugged in the appropriate testing in the advsimd-intrinsics.exp
    too.

    Bootstrapped and tested on aarch64-none-linux-gnu.
    Tested advsimd-intrinsics.exp on arm-none-eabi too to make sure arm
    testing isn't affected.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vreinterpretq_f64_p128,
            vreinterpretq_p128_f64): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
            (clean_results): Add float64x2_t cleanup.
            (DECL_VARIABLE_128BITS_VARIANTS): Add float64x2_t variable.
            * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Add
            testing of vreinterpretq_f64_p128, vreinterpretq_p128_f64.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #38 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:11e0e5fa724f9f6f979abe537d6485850abfe4d9

commit r8-10530-g11e0e5fa724f9f6f979abe537d6485850abfe4d9
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Mon May 21 10:33:30 2018 +0000

    Add missing AArch64 NEON instrinctics for Armv8.2-a to Armv8.4-a

    This patch adds the missing neon intrinsics for all 128 bit vector Integer
modes for the
    three-way XOR and negate and xor instructions for Arm8.2-a to Armv8.4-a.

    gcc/
            PR target/71233
            * config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to
            eor3q<mode>4.
            (aarch64_bcaxqv8hi): Change to bcaxq<mode>4.
            * config/aarch64/aarch64-simd-builtins.def (veor3q_u8, veor3q_u32,
            veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64,
vbcaxq_u8,
            vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
            vbcaxq_s64): New.
            * config/aarch64/arm_neon.h: Likewise.
            * config/aarch64/iterators.md (VQ_I): New.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/sha3.h (veor3q_u8, veor3q_u32,
            veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64,
vbcaxq_u8,
            vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
            vbcaxq_s64): New.
            * gcc.target/aarch64/sha3_1.c: Likewise.
            * gcc.target/aarch64/sha3_2.c: Likewise.
            * gcc.target/aarch64/sha3_3.c: Likewise.

    (cherry picked from commit d21052ebd7ac9d545a26dde3229c57f872c1d5f3)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #39 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:7409639ab568d0d4babcc17370816a2ddd112b72

commit r8-10531-g7409639ab568d0d4babcc17370816a2ddd112b72
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Mon Feb 25 17:46:16 2019 +0000

    AArch64: Update Armv8.4-a's FP16 FML intrinsics

    This patch updates the Armv8.4-a FP16 FML intrinsics's suffixes from u32 to
f16
    to be more consistent with the naming convention for intrinsics.

    The specifications for these intrinsics have not been published yet so we
do
    not need to maintain the old names.

    The patch was created with the following script:

    grep -lIE "(vfml[as].+)_u32" -r gcc/ | grep -iEv ".+Changelog.*" \
      | xargs sed -i -E -e "s/(vfml[as].+)_u32/\1_f16/g"

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vfmlal_low_u32, vfmlsl_low_u32,
            vfmlalq_low_u32, vfmlslq_low_u32, vfmlal_high_u32, vfmlsl_high_u32,
            vfmlalq_high_u32, vfmlslq_high_u32, vfmlal_lane_low_u32,
            vfmlsl_lane_low_u32, vfmlal_laneq_low_u32, vfmlsl_laneq_low_u32,
            vfmlalq_lane_low_u32, vfmlslq_lane_low_u32, vfmlalq_laneq_low_u32,
            vfmlslq_laneq_low_u32, vfmlal_lane_high_u32, vfmlsl_lane_high_u32,
            vfmlal_laneq_high_u32, vfmlsl_laneq_high_u32,
vfmlalq_lane_high_u32,
            vfmlslq_lane_high_u32, vfmlalq_laneq_high_u32,
vfmlslq_laneq_high_u32):
            Rename ...
            (vfmlal_low_f16, vfmlsl_low_f16, vfmlalq_low_f16, vfmlslq_low_f16,
            vfmlal_high_f16, vfmlsl_high_f16, vfmlalq_high_f16,
vfmlslq_high_f16,
            vfmlal_lane_low_f16, vfmlsl_lane_low_f16, vfmlal_laneq_low_f16,
            vfmlsl_laneq_low_f16, vfmlalq_lane_low_f16, vfmlslq_lane_low_f16,
            vfmlalq_laneq_low_f16, vfmlslq_laneq_low_f16, vfmlal_lane_high_f16,
            vfmlsl_lane_high_f16, vfmlal_laneq_high_f16, vfmlsl_laneq_high_f16,
            vfmlalq_lane_high_f16, vfmlslq_lane_high_f16,
vfmlalq_laneq_high_f16,
            vfmlslq_laneq_high_f16): ... To this.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/fp16_fmul_high.h (test_vfmlal_high_u32,
            test_vfmlalq_high_u32, test_vfmlsl_high_u32,
test_vfmlslq_high_u32):
            Rename ...
            (test_vfmlal_high_f16, test_vfmlalq_high_f16, test_vfmlsl_high_f16,
            test_vfmlslq_high_f16): ... To this.
            * gcc.target/aarch64/fp16_fmul_lane_high.h
(test_vfmlal_lane_high_u32,
            tets_vfmlsl_lane_high_u32, test_vfmlal_laneq_high_u32,
            test_vfmlsl_laneq_high_u32, test_vfmlalq_lane_high_u32,
            test_vfmlslq_lane_high_u32, test_vfmlalq_laneq_high_u32,
            test_vfmlslq_laneq_high_u32): Rename ...
            (test_vfmlal_lane_high_f16, tets_vfmlsl_lane_high_f16,
            test_vfmlal_laneq_high_f16, test_vfmlsl_laneq_high_f16,
            test_vfmlalq_lane_high_f16, test_vfmlslq_lane_high_f16,
            test_vfmlalq_laneq_high_f16, test_vfmlslq_laneq_high_f16): ... To
this.
            * gcc.target/aarch64/fp16_fmul_lane_low.h
(test_vfmlal_lane_low_u32,
            test_vfmlsl_lane_low_u32, test_vfmlal_laneq_low_u32,
            test_vfmlsl_laneq_low_u32, test_vfmlalq_lane_low_u32,
            test_vfmlslq_lane_low_u32, test_vfmlalq_laneq_low_u32,
            test_vfmlslq_laneq_low_u32): Rename ...
            (test_vfmlal_lane_low_f16, test_vfmlsl_lane_low_f16,
            test_vfmlal_laneq_low_f16, test_vfmlsl_laneq_low_f16,
            test_vfmlalq_lane_low_f16, test_vfmlslq_lane_low_f16,
            test_vfmlalq_laneq_low_f16, test_vfmlslq_laneq_low_f16): ... To
this.
            * gcc.target/aarch64/fp16_fmul_low.h (test_vfmlal_low_u32,
            test_vfmlalq_low_u32, test_vfmlsl_low_u32, test_vfmlslq_low_u32):
            Rename ...
            (test_vfmlal_low_f16, test_vfmlalq_low_f16, test_vfmlsl_low_f16,
            test_vfmlslq_low_f16): ... To This.
            * lib/target-supports.exp
            (check_effective_target_arm_fp16fml_neon_ok_nocache): Update test.

    (cherry picked from commit 9d04c986b6faed878dbcc86d2f9392a721a3936e)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #40 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:6f06be1769d45359940c60517f9d55bedd3cb1f4

commit r9-8936-g6f06be1769d45359940c60517f9d55bedd3cb1f4
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 3 08:40:30 2019 +0000

    Add support for __jcvt intrinsic

    This patch implements the __jcvt ACLE intrinsic [1] that maps down to the
FJCVTZS [2] instruction from Armv8.3-a.
    No fancy mode iterators or nothing. Just a single builtin, UNSPEC and
define_insn and the associate plumbing.
    This patch also defines __ARM_FEATURE_JCVT to indicate when the intrinsic
is available.

    [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics
    [2]
https://developer.arm.com/docs/ddi0596/latest/simd-and-floating-point-instructions-alphabetic-order/fjcvtzs-floating-point-javascript-convert-to-signed-fixed-point-rounding-toward-zero

    gcc/
            PR target/71233
            * config/aarch64/aarch64.md (UNSPEC_FJCVTZS): Define.
            (aarch64_fjcvtzs): New define_insn.
            * config/aarch64/aarch64.h (TARGET_JSCVT): Define.
            * config/aarch64/aarch64-builtins.c (aarch64_builtins):
            Add AARCH64_JSCVT.
            (aarch64_init_builtins): Initialize __builtin_aarch64_jcvtzs.
            (aarch64_expand_builtin): Handle AARCH64_JSCVT.
            * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
            __ARM_FEATURE_JCVT where appropriate.
            * config/aarch64/arm_acle.h (__jcvt): Define.
            * doc/sourcebuild.texi (aarch64_fjcvtzs_hw) Document new
            target supports option.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/acle/jcvt_1.c: New test.
            * gcc.target/aarch64/acle/jcvt_2.c: New testcase.
            * lib/target-supports.exp
            (check_effective_target_aarch64_fjcvtzs_hw): Add new check for
            FJCVTZS hw.

    Co-Authored-By: Andrea Corallo  <andrea.corallo@arm.com>

    (cherry picked from commit e1d5d19ec4f84b67ac693fef5b2add7dc9cf056d)
    (cherry picked from commit 2c62952f8160bdc8d4111edb34a4bc75096c1e05)
    (cherry picked from commit d2b86e14c14020f3e119ab8f462e2a91bd7d46e5)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #41 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:a8ec9cc2241f4e0c387e78f23bae0100c74de6a8

commit r8-10532-ga8ec9cc2241f4e0c387e78f23bae0100c74de6a8
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 3 08:40:30 2019 +0000

    Add support for __jcvt intrinsic

    This patch implements the __jcvt ACLE intrinsic [1] that maps down to the
FJCVTZS [2] instruction from Armv8.3-a.
    No fancy mode iterators or nothing. Just a single builtin, UNSPEC and
define_insn and the associate plumbing.
    This patch also defines __ARM_FEATURE_JCVT to indicate when the intrinsic
is available.

    [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics
    [2]
https://developer.arm.com/docs/ddi0596/latest/simd-and-floating-point-instructions-alphabetic-order/fjcvtzs-floating-point-javascript-convert-to-signed-fixed-point-rounding-toward-zero

    gcc/
            PR target/71233
            * config/aarch64/aarch64.md (UNSPEC_FJCVTZS): Define.
            (aarch64_fjcvtzs): New define_insn.
            * config/aarch64/aarch64.h (TARGET_JSCVT): Define.
            * config/aarch64/aarch64-builtins.c (aarch64_builtins):
            Add AARCH64_JSCVT.
            (aarch64_init_builtins): Initialize __builtin_aarch64_jcvtzs.
            (aarch64_expand_builtin): Handle AARCH64_JSCVT.
            * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
            __ARM_FEATURE_JCVT where appropriate.
            * config/aarch64/arm_acle.h (__jcvt): Define.
            * doc/sourcebuild.texi (aarch64_fjcvtzs_hw) Document new
            target supports option.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/acle/jcvt_1.c: New test.
            * gcc.target/aarch64/acle/jcvt_2.c: New testcase.
            * lib/target-supports.exp
            (check_effective_target_aarch64_fjcvtzs_hw): Add new check for
            FJCVTZS hw.

    Co-Authored-By: Andrea Corallo  <andrea.corallo@arm.com>

    (cherry picked from commit e1d5d19ec4f84b67ac693fef5b2add7dc9cf056d)
    (cherry picked from commit 2c62952f8160bdc8d4111edb34a4bc75096c1e05)
    (cherry picked from commit d2b86e14c14020f3e119ab8f462e2a91bd7d46e5)
    (cherry picked from commit 58ae77d3ba70a2b9ccc90a90f3f82cf46239d5f1)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #42 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:4fb606b503780b91ad79c203003dc41a32cfbab7

commit r9-8939-g4fb606b503780b91ad79c203003dc41a32cfbab7
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Mon Oct 21 10:52:05 2019 +0000

    Implement __rndr, __rndrrs intrinsics

    This patch implements the recently published[1] __rndr and __rndrrs
    intrinsics used to access the RNG in Armv8.5-A.
    The __rndrrs intrinsics can be used to reseed the generator too.
    They are guarded by the __ARM_FEATURE_RNG feature macro.
    A quirk with these intrinsics is that they store the random number in
    their pointer argument and return a status
    code if the generation succeeded.

    The instructions themselves write the CC flags indicating the success of
    the operation that we can then read with a CSET.
    Therefore this implementation makes use of the IGNORE indicator to the
    builtin expand machinery to avoid generating
    the CSET if its result is unused (the CC reg clobbering effect is still
    reflected in the pattern).
    I've checked that using unspec_volatile prevents undesirable CSEing of
    the instructions.

    [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics

    gcc/
            PR target/71233
            * config/aarch64/aarch64.md (UNSPEC_RNDR, UNSPEC_RNDRRS):
            Define.
            (aarch64_rndr): New define_insn.
            (aarch64_rndrrs): Likewise.
            * config/aarch64/aarch64.h (AARCH64_ISA_RNG): Define.
            (TARGET_RNG): Likewise.
            * config/aarch64/aarch64-builtins.c (enum aarch64_builtins):
            Add AARCH64_BUILTIN_RNG_RNDR, AARCH64_BUILTIN_RNG_RNDRRS.
            (aarch64_init_rng_builtins): Define.
            (aarch64_init_builtins): Call aarch64_init_rng_builtins.
            (aarch64_expand_rng_builtin): Define.
            (aarch64_expand_builtin): Use IGNORE argument, handle
            RNG builtins.
            * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins):
            Define __ARM_FEATURE_RNG when TARGET_RNG.
            * config/aarch64/arm_acle.h (__rndr, __rndrrs): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/acle/rng_1.c: New test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #43 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:26020c849802a03f7a0634636d752ffbc7729096

commit r8-10535-g26020c849802a03f7a0634636d752ffbc7729096
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Mon Oct 21 10:52:05 2019 +0000

    AArch64: Implement __rndr, __rndrrs intrinsics

    This patch implements the recently published[1] __rndr and __rndrrs
    intrinsics used to access the RNG in Armv8.5-A.
    The __rndrrs intrinsics can be used to reseed the generator too.
    They are guarded by the __ARM_FEATURE_RNG feature macro.
    A quirk with these intrinsics is that they store the random number in
    their pointer argument and return a status
    code if the generation succeeded.

    The instructions themselves write the CC flags indicating the success of
    the operation that we can then read with a CSET.
    Therefore this implementation makes use of the IGNORE indicator to the
    builtin expand machinery to avoid generating
    the CSET if its result is unused (the CC reg clobbering effect is still
    reflected in the pattern).
    I've checked that using unspec_volatile prevents undesirable CSEing of
    the instructions.

    [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics

    gcc/
            PR target/71233
            * config/aarch64/aarch64.md (UNSPEC_RNDR, UNSPEC_RNDRRS):
            Define.
            (aarch64_rndr): New define_insn.
            (aarch64_rndrrs): Likewise.
            * config/aarch64/aarch64.h (AARCH64_ISA_RNG): Define.
            (TARGET_RNG): Likewise.
            (AARCH64_FL_RNG): Likewise.
            * config/aarch64/aarch64-option-extensions.def (rng): Define.
            * config/aarch64/aarch64-builtins.c (enum aarch64_builtins):
            Add AARCH64_BUILTIN_RNG_RNDR, AARCH64_BUILTIN_RNG_RNDRRS.
            (aarch64_init_rng_builtins): Define.
            (aarch64_init_builtins): Call aarch64_init_rng_builtins.
            (aarch64_expand_rng_builtin): Define.
            (aarch64_expand_builtin): Use IGNORE argument, handle
            RNG builtins.
            * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins):
            Define __ARM_FEATURE_RNG when TARGET_RNG.
            * config/aarch64/arm_acle.h (__rndr, __rndrrs): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/acle/rng_1.c: New test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #44 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:8c775bf447e190024fa08c55e38db94dd013a393

commit r11-3455-g8c775bf447e190024fa08c55e38db94dd013a393
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Sep 25 10:40:18 2020 +0000

    testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,uzp,zip}_half.c

    Since r11-3402 (g:65c9878641cbe0ed898aa7047b7b994e9d4a5bb1), the
    vtrn_half, vuzp_half and vzip_half started failing with

    vtrn_half.c:76:17: error: redeclaration of 'vector_float64x2' with no
linkage
    vtrn_half.c:77:17: error: redeclaration of 'vector2_float64x2' with no
linkage
    vtrn_half.c:80:17: error: redeclaration of 'vector_res_float64x2' with no
linkage

    This is because r11-3402 now always declares float64x2 variables for
    aarch64, leading to a duplicate declaration in these testcases.

    The fix is simply to remove these now useless declarations.

    These tests are skipped on arm*, so there is no impact on that target.

    2020-09-25  Christophe Lyon  <christophe.lyon@linaro.org>

            gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: Remove
            declarations of vector, vector2, vector_res for float64x2 type.
            * gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: Likewise.
            * gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: Likewise.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #45 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:1788d74b05b7936e9e8dd01a8f66701ad2bc2951

commit r8-10536-g1788d74b05b7936e9e8dd01a8f66701ad2bc2951
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Thu Jan 10 03:30:59 2019 +0000

    AArch64: Implement Armv8.3-a complex arithmetic intrinsics

    I'd like to backport some patches from Tamar in GCC 9 to GCC 8 that
implement the complex arithmetic intrinsics for Advanced SIMD.
    These should have been present in GCC 8 that gained support for Armv8.3-a.

    There were 4 follow-up fixes that I've rolled into the one commit.

    Bootstrapped and tested on aarch64-none-linux-gnu and
arm-none-linux-gnueabihf on the GCC 8 branch.

    gcc/
            PR target/71233
            * config/aarch64/aarch64-builtins.c (enum aarch64_type_qualifiers):
            Add qualifier_lane_pair_index.
            (emit-rtl.h): Include.
            (TYPES_QUADOP_LANE_PAIR): New.
            (aarch64_simd_expand_args): Use it.
            (aarch64_simd_expand_builtin): Likewise.
            (AARCH64_SIMD_FCMLA_LANEQ_BUILTINS,
aarch64_fcmla_laneq_builtin_datum): New.
            (FCMLA_LANEQ_BUILTIN, AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
            AARCH64_SIMD_FCMLA_LANEQ_BUILTINS, aarch64_fcmla_lane_builtin_data,
            aarch64_init_fcmla_laneq_builtins, aarch64_expand_fcmla_builtin):
New.
            (aarch64_init_builtins): Add aarch64_init_fcmla_laneq_builtins.
            (aarch64_expand_buildin): Add
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF,
            AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF,
            AARCH64_SIMD_BUILTIN_FCMLA_LANEQ2700_V2SF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V4HF,
            AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V4HF,
AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V4HF,
            AARCH64_SIMD_BUILTIN_FCMLA_LANEQ270_V4HF.
            * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Add
__ARM_FEATURE_COMPLEX.
            * config/aarch64/aarch64-simd-builtins.def (fcadd90, fcadd270,
fcmla0, fcmla90,
            fcmla180, fcmla270, fcmla_lane0, fcmla_lane90, fcmla_lane180,
fcmla_lane270,
            fcmla_laneq0, fcmla_laneq90, fcmla_laneq180, fcmla_laneq270,
            fcmlaq_lane0, fcmlaq_lane90, fcmlaq_lane180, fcmlaq_lane270): New.
            * config/aarch64/aarch64-simd.md (aarch64_fcmla_lane<rot><mode>,
            aarch64_fcmla_laneq<rot>v4hf,
aarch64_fcmlaq_lane<rot><mode>,aarch64_fcadd<rot><mode>,
            aarch64_fcmla<rot><mode>): New.
            * config/aarch64/arm_neon.h:
            (vcadd_rot90_f16): New.
            (vcaddq_rot90_f16): New.
            (vcadd_rot270_f16): New.
            (vcaddq_rot270_f16): New.
            (vcmla_f16): New.
            (vcmlaq_f16): New.
            (vcmla_lane_f16): New.
            (vcmla_laneq_f16): New.
            (vcmlaq_lane_f16): New.
            (vcmlaq_rot90_lane_f16): New.
            (vcmla_rot90_laneq_f16): New.
            (vcmla_rot90_lane_f16): New.
            (vcmlaq_rot90_f16): New.
            (vcmla_rot90_f16): New.
            (vcmlaq_laneq_f16): New.
            (vcmla_rot180_laneq_f16): New.
            (vcmla_rot180_lane_f16): New.
            (vcmlaq_rot180_f16): New.
            (vcmla_rot180_f16): New.
            (vcmlaq_rot90_laneq_f16): New.
            (vcmlaq_rot270_laneq_f16): New.
            (vcmlaq_rot270_lane_f16): New.
            (vcmla_rot270_laneq_f16): New.
            (vcmlaq_rot270_f16): New.
            (vcmla_rot270_f16): New.
            (vcmlaq_rot180_laneq_f16): New.
            (vcmlaq_rot180_lane_f16): New.
            (vcmla_rot270_lane_f16): New.
            (vcadd_rot90_f32): New.
            (vcaddq_rot90_f32): New.
            (vcaddq_rot90_f64): New.
            (vcadd_rot270_f32): New.
            (vcaddq_rot270_f32): New.
            (vcaddq_rot270_f64): New.
            (vcmla_f32): New.
            (vcmlaq_f32): New.
            (vcmlaq_f64): New.
            (vcmla_lane_f32): New.
            (vcmla_laneq_f32): New.
            (vcmlaq_lane_f32): New.
            (vcmlaq_laneq_f32): New.
            (vcmla_rot90_f32): New.
            (vcmlaq_rot90_f32): New.
            (vcmlaq_rot90_f64): New.
            (vcmla_rot90_lane_f32): New.
            (vcmla_rot90_laneq_f32): New.
            (vcmlaq_rot90_lane_f32): New.
            (vcmlaq_rot90_laneq_f32): New.
            (vcmla_rot180_f32): New.
            (vcmlaq_rot180_f32): New.
            (vcmlaq_rot180_f64): New.
            (vcmla_rot180_lane_f32): New.
            (vcmla_rot180_laneq_f32): New.
            (vcmlaq_rot180_lane_f32): New.
            (vcmlaq_rot180_laneq_f32): New.
            (vcmla_rot270_f32): New.
            (vcmlaq_rot270_f32): New.
            (vcmlaq_rot270_f64): New.
            (vcmla_rot270_lane_f32): New.
            (vcmla_rot270_laneq_f32): New.
            (vcmlaq_rot270_lane_f32): New.
            (vcmlaq_rot270_laneq_f32): New.
            * config/aarch64/aarch64.h (TARGET_COMPLEX): New.
            * config/aarch64/iterators.md (UNSPEC_FCADD90, UNSPEC_FCADD270,
            UNSPEC_FCMLA, UNSPEC_FCMLA90, UNSPEC_FCMLA180, UNSPEC_FCMLA270):
New.
            (FCADD, FCMLA): New.
            (rot): New.
            (FCMLA_maybe_lane): New.
            * config/arm/types.md (neon_fcadd, neon_fcmla): New.

    gcc/testsuite/
            PR target/71233
            * lib/target-supports.exp
            (check_effective_target_arm_v8_3a_complex_neon_ok_nocache,
            check_effective_target_arm_v8_3a_complex_neon_ok,
            add_options_for_arm_v8_3a_complex_neon,
            check_effective_target_arm_v8_3a_complex_neon_hw,
            check_effective_target_vect_complex_rot_N): New.
            * gcc.target/aarch64/advsimd-intrinsics/vector-complex.c: New test.
            * gcc.target/aarch64/advsimd-intrinsics/vector-complex_f16.c: New
test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #46 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:117b23e43f765cadbf3ca4b80602dc158789675b

commit r10-8808-g117b23e43f765cadbf3ca4b80602dc158789675b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 11:58:36 2020 +0100

    AArch64: Implement poly-type vadd intrinsics

    This implements the vadd[p]_p* intrinsics.
    In terms of functionality they are aliases of veor operations on the
relevant unsigned types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vadd_p8, vadd_p16, vadd_p64, vaddq_p8,
            vaddq_p16, vaddq_p64, vaddq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vadd_poly_1.c: New test.

    (cherry picked from commit fa9ad35dae03dcb20c4ccb50ba1b351a8ab77970)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #47 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:b8442a7c4c09375b76fa174313205fa7fcbfb016

commit r10-8809-gb8442a7c4c09375b76fa174313205fa7fcbfb016
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:00:38 2020 +0100

    AArch64: Implement missing vceq*_p* intrinsics

    This patch implements some missing vceq* intrinsics on poly types.
    The behaviour is to produce the appropriate CMEQ instruction as for the
unsigned types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vceqq_p64, vceqz_p64, vceqzq_p64):
Define.

    gcc/testsuite/

            PR target/71233
            * gcc.target/aarch64/simd/vceq_poly_1.c: New test.

    (cherry picked from commit d4703be185b422f637deebd3bb9222a41c8023d6)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #48 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:34db2d23439b39d2c7e5760f0f7de41f98b08c80

commit r10-8810-g34db2d23439b39d2c7e5760f0f7de41f98b08c80
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:03:49 2020 +0100

    AArch64: Implement missing vcls intrinsics on unsigned types

    This patch implements some missing intrinsics that perform a CLS on
unsigned SIMD types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vcls_u8, vcls_u16, vcls_u32,
            vclsq_u8, vclsq_u16, vclsq_u32): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vcls_unsigned_1.c: New test.

    (cherry picked from commit 30957092db46d8798e632feefb5df634488dbb33)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #49 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:bc04ceb7b94d9144ac923210f1affaa3dfed0725

commit r10-8811-gbc04ceb7b94d9144ac923210f1affaa3dfed0725
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 10:29:17 2020 +0100

    AArch64: Implement vstrq_p128 intrinsic

    This patch implements the missing vstrq_p128 intrinsic.
    It just performs a store of the poly128_t argument to a memory location.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vstrq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vstrq_p128_1.c: New test.

    (cherry picked from commit d23ea1e865301cd45f14ccbdb0bca49251fde9e1)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #50 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:1c0679d6b5d12fb9d708442a8af725136a17f9cf

commit r10-8812-g1c0679d6b5d12fb9d708442a8af725136a17f9cf
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 10:32:42 2020 +0100

    AArch64: Implement vldrq_p128 intrinsic

    This patch implements the missing vldrq_p128 intrinsic that just loads from
the appropriate pointer.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vldrq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vldrq_p128_1.c: New test.

    (cherry picked from commit f2868e4bcff2c7b882d01231f039459c00e59d7b)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #51 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:5b9f76b95528775b3f09d151c56ff80747109498

commit r10-8813-g5b9f76b95528775b3f09d151c56ff80747109498
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 11:07:50 2020 +0100

    AArch64: Implement missing _p64 intrinsics for vector permutes

    This patch implements some missing vector permute intrinsics operating on
poly64x2_t types.
    They are implemented identically to their uint64x2_t brethren.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vtrn1q_p64, vtrn2q_p64, vuzp1q_p64,
            vuzp2q_p64, vzip1q_p64, vzip2q_p64): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/trn_zip_p64_1.c: New test.

    (cherry picked from commit e8e818399d70c5a5a3d30a54d305c6e2b92e2c66)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #52 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:858cfd55807883dfe1e051ad7d67d9c0449728f9

commit r10-8814-g858cfd55807883dfe1e051ad7d67d9c0449728f9
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 12:02:29 2020 +0100

    AArch64: Implement missing vrndns_f32 intrinsic

    This patch implements the missing vrndns_f32 intrinsic. This operates on a
scalar float32_t value.
    It can be mapped down to a __builtin_aarch64_frintnsf builtin.

    This patch does that.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/aarch64-simd-builtins.def (frintn): Use
BUILTIN_VHSDF_HSDF
            for modes.  Remove explicit hf instantiation.
            * config/aarch64/arm_neon.h (vrndns_f32): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vrndns_f32_1.c: New test.

    (cherry picked from commit 02b5377b3766804059b7824330d33d0e1cef2e5b)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #53 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:677f34508f1c8fba6a52c77f83eca08b6762ed28

commit r10-8815-g677f34508f1c8fba6a52c77f83eca08b6762ed28
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 17:37:58 2020 +0100

    AArch64: Implement missing p128<->f64 reinterpret intrinsics

    This patch implements the missing reinterprets to and from poly128_t and
    float64x2_t.
    I've plugged in the appropriate testing in the advsimd-intrinsics.exp
    too.

    Bootstrapped and tested on aarch64-none-linux-gnu.
    Tested advsimd-intrinsics.exp on arm-none-eabi too to make sure arm
    testing isn't affected.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vreinterpretq_f64_p128,
            vreinterpretq_p128_f64): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
            (clean_results): Add float64x2_t cleanup.
            (DECL_VARIABLE_128BITS_VARIANTS): Add float64x2_t variable.
            * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Add
            testing of vreinterpretq_f64_p128, vreinterpretq_p128_f64.

    (cherry picked from commit 65c9878641cbe0ed898aa7047b7b994e9d4a5bb1)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #54 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:a6c47f4ce26639bfbc72821ae629b9af7744a9d7

commit r10-8816-ga6c47f4ce26639bfbc72821ae629b9af7744a9d7
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Sep 25 10:40:18 2020 +0000

    testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,uzp,zip}_half.c

    Since r11-3402 (g:65c9878641cbe0ed898aa7047b7b994e9d4a5bb1), the
    vtrn_half, vuzp_half and vzip_half started failing with

    vtrn_half.c:76:17: error: redeclaration of 'vector_float64x2' with no
linkage
    vtrn_half.c:77:17: error: redeclaration of 'vector2_float64x2' with no
linkage
    vtrn_half.c:80:17: error: redeclaration of 'vector_res_float64x2' with no
linkage

    This is because r11-3402 now always declares float64x2 variables for
    aarch64, leading to a duplicate declaration in these testcases.

    The fix is simply to remove these now useless declarations.

    These tests are skipped on arm*, so there is no impact on that target.

    2020-09-25  Christophe Lyon  <christophe.lyon@linaro.org>

            gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: Remove
            declarations of vector, vector2, vector_res for float64x2 type.
            * gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: Likewise.
            * gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: Likewise.

    (cherry picked from commit 8c775bf447e190024fa08c55e38db94dd013a393)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #55 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:48e274be62b924379541ae0321b82862f572b973

commit r9-8946-g48e274be62b924379541ae0321b82862f572b973
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 11:58:36 2020 +0100

    AArch64: Implement poly-type vadd intrinsics

    This implements the vadd[p]_p* intrinsics.
    In terms of functionality they are aliases of veor operations on the
relevant unsigned types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vadd_p8, vadd_p16, vadd_p64, vaddq_p8,
            vaddq_p16, vaddq_p64, vaddq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vadd_poly_1.c: New test.

    (cherry picked from commit fa9ad35dae03dcb20c4ccb50ba1b351a8ab77970)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #56 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:11874a0d4033908e596181a17dab5444271f892b

commit r9-8947-g11874a0d4033908e596181a17dab5444271f892b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:00:38 2020 +0100

    AArch64: Implement missing vceq*_p* intrinsics

    This patch implements some missing vceq* intrinsics on poly types.
    The behaviour is to produce the appropriate CMEQ instruction as for the
unsigned types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vceqq_p64, vceqz_p64, vceqzq_p64):
Define.

    gcc/testsuite/

            PR target/71233
            * gcc.target/aarch64/simd/vceq_poly_1.c: New test.

    (cherry picked from commit d4703be185b422f637deebd3bb9222a41c8023d6)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #57 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:6f189fa29bc90c658ce1df33774a04d4956dcc27

commit r9-8948-g6f189fa29bc90c658ce1df33774a04d4956dcc27
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:03:49 2020 +0100

    AArch64: Implement missing vcls intrinsics on unsigned types

    This patch implements some missing intrinsics that perform a CLS on
unsigned SIMD types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vcls_u8, vcls_u16, vcls_u32,
            vclsq_u8, vclsq_u16, vclsq_u32): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vcls_unsigned_1.c: New test.

    (cherry picked from commit 30957092db46d8798e632feefb5df634488dbb33)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #58 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:9f7c4bb47c97aa6cd68bd48f6f2129e19f01c892

commit r9-8949-g9f7c4bb47c97aa6cd68bd48f6f2129e19f01c892
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 10:29:17 2020 +0100

    AArch64: Implement vstrq_p128 intrinsic

    This patch implements the missing vstrq_p128 intrinsic.
    It just performs a store of the poly128_t argument to a memory location.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vstrq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vstrq_p128_1.c: New test.

    (cherry picked from commit d23ea1e865301cd45f14ccbdb0bca49251fde9e1)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #59 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:0d27e8eb8dc8ed28fdf4d6876d7f6f0610273198

commit r9-8950-g0d27e8eb8dc8ed28fdf4d6876d7f6f0610273198
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 10:32:42 2020 +0100

    AArch64: Implement vldrq_p128 intrinsic

    This patch implements the missing vldrq_p128 intrinsic that just loads from
the appropriate pointer.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vldrq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vldrq_p128_1.c: New test.

    (cherry picked from commit f2868e4bcff2c7b882d01231f039459c00e59d7b)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #60 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:23b4d65ef54b9ad8eb5cca65b7412d46f35d913f

commit r9-8951-g23b4d65ef54b9ad8eb5cca65b7412d46f35d913f
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 11:07:50 2020 +0100

    AArch64: Implement missing _p64 intrinsics for vector permutes

    This patch implements some missing vector permute intrinsics operating on
poly64x2_t types.
    They are implemented identically to their uint64x2_t brethren.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vtrn1q_p64, vtrn2q_p64, vuzp1q_p64,
            vuzp2q_p64, vzip1q_p64, vzip2q_p64): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/trn_zip_p64_1.c: New test.

    (cherry picked from commit e8e818399d70c5a5a3d30a54d305c6e2b92e2c66)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #61 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:61291c4b7d429ddd12536732759bd56708e78e14

commit r9-8952-g61291c4b7d429ddd12536732759bd56708e78e14
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 12:02:29 2020 +0100

    AArch64: Implement missing vrndns_f32 intrinsic

    This patch implements the missing vrndns_f32 intrinsic. This operates on a
scalar float32_t value.
    It can be mapped down to a __builtin_aarch64_frintnsf builtin.

    This patch does that.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/aarch64-simd-builtins.def (frintn): Use
BUILTIN_VHSDF_HSDF
            for modes.  Remove explicit hf instantiation.
            * config/aarch64/arm_neon.h (vrndns_f32): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vrndns_f32_1.c: New test.

    (cherry picked from commit 02b5377b3766804059b7824330d33d0e1cef2e5b)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #62 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:803f597d3125bfd67d29a11c118e131353ee314e

commit r9-8953-g803f597d3125bfd67d29a11c118e131353ee314e
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 17:37:58 2020 +0100

    AArch64: Implement missing p128<->f64 reinterpret intrinsics

    This patch implements the missing reinterprets to and from poly128_t and
    float64x2_t.
    I've plugged in the appropriate testing in the advsimd-intrinsics.exp
    too.

    Bootstrapped and tested on aarch64-none-linux-gnu.
    Tested advsimd-intrinsics.exp on arm-none-eabi too to make sure arm
    testing isn't affected.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vreinterpretq_f64_p128,
            vreinterpretq_p128_f64): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
            (clean_results): Add float64x2_t cleanup.
            (DECL_VARIABLE_128BITS_VARIANTS): Add float64x2_t variable.
            * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Add
            testing of vreinterpretq_f64_p128, vreinterpretq_p128_f64.

    (cherry picked from commit 65c9878641cbe0ed898aa7047b7b994e9d4a5bb1)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #63 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:3fa772a7acfea62a01fb36d1451c8be9c54ba7da

commit r9-8954-g3fa772a7acfea62a01fb36d1451c8be9c54ba7da
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Sep 25 10:40:18 2020 +0000

    testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,uzp,zip}_half.c

    Since r11-3402 (g:65c9878641cbe0ed898aa7047b7b994e9d4a5bb1), the
    vtrn_half, vuzp_half and vzip_half started failing with

    vtrn_half.c:76:17: error: redeclaration of 'vector_float64x2' with no
linkage
    vtrn_half.c:77:17: error: redeclaration of 'vector2_float64x2' with no
linkage
    vtrn_half.c:80:17: error: redeclaration of 'vector_res_float64x2' with no
linkage

    This is because r11-3402 now always declares float64x2 variables for
    aarch64, leading to a duplicate declaration in these testcases.

    The fix is simply to remove these now useless declarations.

    These tests are skipped on arm*, so there is no impact on that target.

    2020-09-25  Christophe Lyon  <christophe.lyon@linaro.org>

            gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: Remove
            declarations of vector, vector2, vector_res for float64x2 type.
            * gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: Likewise.
            * gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: Likewise.

    (cherry picked from commit 8c775bf447e190024fa08c55e38db94dd013a393)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #64 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:3c21a2f28014cd3bbfaee975a466dc3488052060

commit r8-10543-g3c21a2f28014cd3bbfaee975a466dc3488052060
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 11:58:36 2020 +0100

    AArch64: Implement poly-type vadd intrinsics

    This implements the vadd[p]_p* intrinsics.
    In terms of functionality they are aliases of veor operations on the
relevant unsigned types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vadd_p8, vadd_p16, vadd_p64, vaddq_p8,
            vaddq_p16, vaddq_p64, vaddq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vadd_poly_1.c: New test.

    (cherry picked from commit fa9ad35dae03dcb20c4ccb50ba1b351a8ab77970)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #65 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:e9ed4afbb6778dedfb1efa0ba92429a51d4d049b

commit r8-10544-ge9ed4afbb6778dedfb1efa0ba92429a51d4d049b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:00:38 2020 +0100

    AArch64: Implement missing vceq*_p* intrinsics

    This patch implements some missing vceq* intrinsics on poly types.
    The behaviour is to produce the appropriate CMEQ instruction as for the
unsigned types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vceqq_p64, vceqz_p64, vceqzq_p64):
Define.

    gcc/testsuite/

            PR target/71233
            * gcc.target/aarch64/simd/vceq_poly_1.c: New test.

    (cherry picked from commit d4703be185b422f637deebd3bb9222a41c8023d6)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #66 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:fd250940d0e3dd17302eb5e2653255c9189bfd70

commit r8-10545-gfd250940d0e3dd17302eb5e2653255c9189bfd70
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Tue Sep 22 12:03:49 2020 +0100

    AArch64: Implement missing vcls intrinsics on unsigned types

    This patch implements some missing intrinsics that perform a CLS on
unsigned SIMD types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vcls_u8, vcls_u16, vcls_u32,
            vclsq_u8, vclsq_u16, vclsq_u32): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vcls_unsigned_1.c: New test.

    (cherry picked from commit 30957092db46d8798e632feefb5df634488dbb33)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #67 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:c0817ceebffa0be66b39c874a5da408404330b42

commit r8-10546-gc0817ceebffa0be66b39c874a5da408404330b42
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 10:29:17 2020 +0100

    AArch64: Implement vstrq_p128 intrinsic

    This patch implements the missing vstrq_p128 intrinsic.
    It just performs a store of the poly128_t argument to a memory location.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vstrq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vstrq_p128_1.c: New test.

    (cherry picked from commit d23ea1e865301cd45f14ccbdb0bca49251fde9e1)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #68 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:a45e419416c641b7be5d4f4eb877fa390349c004

commit r8-10547-ga45e419416c641b7be5d4f4eb877fa390349c004
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 10:32:42 2020 +0100

    AArch64: Implement vldrq_p128 intrinsic

    This patch implements the missing vldrq_p128 intrinsic that just loads from
the appropriate pointer.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vldrq_p128): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vldrq_p128_1.c: New test.

    (cherry picked from commit f2868e4bcff2c7b882d01231f039459c00e59d7b)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #69 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:99a8808add97c61b64a4cb979e4616731b86e58b

commit r8-10548-g99a8808add97c61b64a4cb979e4616731b86e58b
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 11:07:50 2020 +0100

    AArch64: Implement missing _p64 intrinsics for vector permutes

    This patch implements some missing vector permute intrinsics operating on
poly64x2_t types.
    They are implemented identically to their uint64x2_t brethren.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vtrn1q_p64, vtrn2q_p64, vuzp1q_p64,
            vuzp2q_p64, vzip1q_p64, vzip2q_p64): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/trn_zip_p64_1.c: New test.

    (cherry picked from commit e8e818399d70c5a5a3d30a54d305c6e2b92e2c66)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #70 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:852423cd68b403d09a14f6436080243c609a57a8

commit r8-10549-g852423cd68b403d09a14f6436080243c609a57a8
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 12:02:29 2020 +0100

    AArch64: Implement missing vrndns_f32 intrinsic

    This patch implements the missing vrndns_f32 intrinsic. This operates on a
scalar float32_t value.
    It can be mapped down to a __builtin_aarch64_frintnsf builtin.

    This patch does that.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/aarch64-simd-builtins.def (frintn): Use
BUILTIN_VHSDF_HSDF
            for modes.  Remove explicit hf instantiation.
            * config/aarch64/arm_neon.h (vrndns_f32): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vrndns_f32_1.c: New test.

    (cherry picked from commit 02b5377b3766804059b7824330d33d0e1cef2e5b)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #71 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:3489c06cccb60c1af4c66aff82b670fb39f36266

commit r8-10550-g3489c06cccb60c1af4c66aff82b670fb39f36266
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Sep 23 17:37:58 2020 +0100

    AArch64: Implement missing p128<->f64 reinterpret intrinsics

    This patch implements the missing reinterprets to and from poly128_t and
    float64x2_t.
    I've plugged in the appropriate testing in the advsimd-intrinsics.exp
    too.

    Bootstrapped and tested on aarch64-none-linux-gnu.
    Tested advsimd-intrinsics.exp on arm-none-eabi too to make sure arm
    testing isn't affected.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vreinterpretq_f64_p128,
            vreinterpretq_p128_f64): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
            (clean_results): Add float64x2_t cleanup.
            (DECL_VARIABLE_128BITS_VARIANTS): Add float64x2_t variable.
            * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Add
            testing of vreinterpretq_f64_p128, vreinterpretq_p128_f64.

    (cherry picked from commit 65c9878641cbe0ed898aa7047b7b994e9d4a5bb1)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #72 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:768c95cc6c84d504cf95fe948d808376628d2fa8

commit r8-10551-g768c95cc6c84d504cf95fe948d808376628d2fa8
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Sep 25 10:40:18 2020 +0000

    testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,uzp,zip}_half.c

    Since r11-3402 (g:65c9878641cbe0ed898aa7047b7b994e9d4a5bb1), the
    vtrn_half, vuzp_half and vzip_half started failing with

    vtrn_half.c:76:17: error: redeclaration of 'vector_float64x2' with no
linkage
    vtrn_half.c:77:17: error: redeclaration of 'vector2_float64x2' with no
linkage
    vtrn_half.c:80:17: error: redeclaration of 'vector_res_float64x2' with no
linkage

    This is because r11-3402 now always declares float64x2 variables for
    aarch64, leading to a duplicate declaration in these testcases.

    The fix is simply to remove these now useless declarations.

    These tests are skipped on arm*, so there is no impact on that target.

    2020-09-25  Christophe Lyon  <christophe.lyon@linaro.org>

            gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: Remove
            declarations of vector, vector2, vector_res for float64x2 type.
            * gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: Likewise.
            * gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: Likewise.

    (cherry picked from commit 8c775bf447e190024fa08c55e38db94dd013a393)

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #73 from Christophe Lyon <clyon at gcc dot gnu.org> ---
As of 2021-01-12 (trunk r11-6612 g:e91910d3576eeac714c93ec25ea3b15012007903),
after applying the recipe from comment #6, the situation is:

* no missing aarch64 intrinsic

* List of A32/A64 intrinsics not present in arm/arm_neon:
vceqq_p64
vceqz_p64
vceqzq_p64
vcopy_lane_p64
vcopy_laneq_p64
vcopyq_lane_p64
vcopyq_laneq_p64
vcvtaq_s32_f32
vcvtaq_u32_f32
vcvta_s32_f32
vcvta_u32_f32
vcvtmq_s32_f32
vcvtmq_u32_f32
vcvtm_s32_f32
vcvtm_u32_f32
vcvtnq_s32_f32
vcvtnq_u32_f32
vcvtn_s32_f32
vcvtn_u32_f32
vcvtpq_s32_f32
vcvtpq_u32_f32
vcvtp_s32_f32
vcvtp_u32_f32
vld1_bf16_x2
vld1_bf16_x4
vld1_dup_bf16
vld1_p64_x2
vld1_p64_x3
vld1_p64_x4
vld1q_bf16_x2
vld1q_bf16_x4
vld1q_dup_bf16
vld1q_p64_x2
vld1q_p64_x3
vld1q_p64_x4
vrndi_f32
vrndiq_f32
vrndn_f64
vrndnq_f64
vrndns_f32
vst1_bf16_x2
vst1_bf16_x3
vst1_bf16_x4
vst1_p64_x2
vst1_p64_x3
vst1_p64_x4
vst1q_bf16_x2
vst1q_bf16_x3
vst1q_bf16_x4
vst1q_p64_x2
vst1q_p64_x4
vtstq_p64


* List of v7/a32/a64 intrinsics not present in arm/arm_neon.h:
vadd_p16
vadd_p64
vadd_p8
vaddq_p128
vaddq_p16
vaddq_p64
vaddq_p8
vclsq_u16
vclsq_u32
vclsq_u8
vcls_u16
vcls_u32
vcls_u8
vfma_n_f32
vfmaq_n_f32
vld1_bf16_x3
vld1_f16_x2
vld1_f16_x3
vld1_f16_x4
vld1_f32_x2
vld1_f32_x3
vld1_f32_x4
vld1_p16_x2
vld1_p16_x3
vld1_p16_x4
vld1_p8_x2
vld1_p8_x3
vld1_p8_x4
vld1q_bf16_x3
vld1q_f16_x2
vld1q_f16_x3
vld1q_f16_x4
vld1q_f32_x2
vld1q_f32_x3
vld1q_f32_x4
vld1q_p16_x2
vld1q_p16_x3
vld1q_p16_x4
vld1q_p8_x2
vld1q_p8_x3
vld1q_p8_x4
vld1q_s16_x2
vld1q_s16_x3
vld1q_s16_x4
vld1q_s32_x2
vld1q_s32_x3
vld1q_s32_x4
vld1q_s64_x2
vld1q_s64_x3
vld1q_s64_x4
vld1q_s8_x2
vld1q_s8_x3
vld1q_s8_x4
vld1q_u16_x2
vld1q_u16_x3
vld1q_u16_x4
vld1q_u32_x2
vld1q_u32_x3
vld1q_u32_x4
vld1q_u64_x2
vld1q_u64_x3
vld1q_u64_x4
vld1q_u8_x2
vld1q_u8_x3
vld1q_u8_x4
vld1_s16_x2
vld1_s16_x3
vld1_s16_x4
vld1_s32_x2
vld1_s32_x3
vld1_s32_x4
vld1_s64_x2
vld1_s64_x3
vld1_s64_x4
vld1_s8_x2
vld1_s8_x3
vld1_s8_x4
vld1_u16_x2
vld1_u16_x3
vld1_u16_x4
vld1_u32_x2
vld1_u32_x3
vld1_u32_x4
vld1_u64_x2
vld1_u64_x3
vld1_u64_x4
vld1_u8_x2
vld1_u8_x3
vld1_u8_x4
vld2q_dup_f16
vld2q_dup_f32
vld2q_dup_p16
vld2q_dup_p8
vld2q_dup_s16
vld2q_dup_s32
vld2q_dup_s8
vld2q_dup_u16
vld2q_dup_u32
vld2q_dup_u8
vld3q_dup_f16
vld3q_dup_f32
vld3q_dup_p16
vld3q_dup_p8
vld3q_dup_s16
vld3q_dup_s32
vld3q_dup_s8
vld3q_dup_u16
vld3q_dup_u32
vld3q_dup_u8
vld4q_dup_f16
vld4q_dup_f32
vld4q_dup_p16
vld4q_dup_p8
vld4q_dup_s16
vld4q_dup_s32
vld4q_dup_s8
vld4q_dup_u16
vld4q_dup_u32
vld4q_dup_u8
vmovn_high_s16
vmovn_high_s32
vmovn_high_s64
vmovn_high_u16
vmovn_high_u32
vmovn_high_u64
vreinterpretq_f64_u64
vst1_f16_x2
vst1_f16_x3
vst1_f16_x4
vst1_f32_x2
vst1_f32_x3
vst1_f32_x4
vst1_p16_x2
vst1_p16_x3
vst1_p16_x4
vst1_p8_x2
vst1_p8_x3
vst1_p8_x4
vst1q_f16_x2
vst1q_f16_x3
vst1q_f16_x4
vst1q_f32_x2
vst1q_f32_x3
vst1q_f32_x4
vst1q_p16_x2
vst1q_p16_x3
vst1q_p16_x4
vst1q_p64_x3
vst1q_p8_x2
vst1q_p8_x3
vst1q_p8_x4
vst1q_s16_x2
vst1q_s16_x3
vst1q_s16_x4
vst1q_s32_x2
vst1q_s32_x3
vst1q_s32_x4
vst1q_s64_x2
vst1q_s64_x3
vst1q_s64_x4
vst1q_s8_x2
vst1q_s8_x3
vst1q_s8_x4
vst1q_u16_x2
vst1q_u16_x3
vst1q_u16_x4
vst1q_u32_x2
vst1q_u32_x3
vst1q_u32_x4
vst1q_u64_x2
vst1q_u64_x3
vst1q_u64_x4
vst1q_u8_x2
vst1q_u8_x3
vst1q_u8_x4
vst1_s16_x2
vst1_s16_x3
vst1_s16_x4
vst1_s32_x2
vst1_s32_x3
vst1_s32_x4
vst1_s64_x2
vst1_s64_x3
vst1_s64_x4
vst1_s8_x2
vst1_s8_x3
vst1_s8_x4
vst1_u16_x2
vst1_u16_x3
vst1_u16_x4
vst1_u32_x2
vst1_u32_x3
vst1_u32_x4
vst1_u64_x2
vst1_u64_x3
vst1_u64_x4
vst1_u8_x2
vst1_u8_x3
vst1_u8_x4
vst3q_lane_p8
vst3q_lane_s8
vst3q_lane_u8

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #74 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:1a6306420090409cb397e2e042256eb1905f415f

commit r11-6711-g1a6306420090409cb397e2e042256eb1905f415f
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Thu Oct 15 17:13:59 2020 +0000

    arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics

    This patch adds implementations for vceqq_p64, vceqz_p64 and
    vceqzq_p64 intrinsics.

    vceqq_p64 uses the existing vceq_p64 after splitting the input vectors
    into their high and low halves.

    vceqz[q] simply call the vceq and vceqq with a second argument equal
    to zero.

    The added (executable) testcases make sure that the poly64x2_t
    variants have results with one element of all zeroes (false) and the
    other element with all bits set to one (true).

    2021-01-15  Christophe Lyon  <christophe.lyon@linaro.org>

            gcc/
            PR target/71233
            * config/arm/arm_neon.h (vceqz_p64, vceqq_p64, vceqzq_p64): New.

            gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/p64_p128.c: Add tests for
            vceqz_p64, vceqq_p64 and vceqzq_p64.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #75 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:63999d751df9bcde4ab9107edb4c635d274b248d

commit r11-6719-g63999d751df9bcde4ab9107edb4c635d274b248d
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Thu Oct 15 17:13:59 2020 +0000

    arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics

    This patch adds implementations for vceqq_p64, vceqz_p64 and
    vceqzq_p64 intrinsics.

    vceqq_p64 uses the existing vceq_p64 after splitting the input vectors
    into their high and low halves.

    vceqz[q] simply call the vceq and vceqq with a second argument equal
    to zero.

    The added (executable) testcases make sure that the poly64x2_t
    variants have results with one element of all zeroes (false) and the
    other element with all bits set to one (true).

    2021-01-15  Christophe Lyon  <christophe.lyon@linaro.org>

            gcc/
            PR target/71233
            * config/arm/arm_neon.h (vceqz_p64, vceqq_p64, vceqzq_p64): New.

            gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/p64_p128.c: Add tests for
            vceqz_p64, vceqq_p64 and vceqzq_p64.
            * gcc.target/arm/simd/vceqz_p64.c: New test.
            * gcc.target/arm/simd/vceqzq_p64.c: New test.

[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED