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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/78904] zero-extracts are not effective
Date: Tue, 14 Nov 2023 17:36:41 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D78904

--- Comment #19 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:b42a09b258c3ed8d1368e0ef0948034dcf0f8ac9

commit r14-5456-gb42a09b258c3ed8d1368e0ef0948034dcf0f8ac9
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue Nov 14 18:34:43 2023 +0100

    i386: Generate strict_low_part QImode insn with high input register

    Following testcase:

    struct S1
    {
      unsigned char val;
      unsigned char pad1;
      unsigned short pad2;
    };

    struct S2
    {
      unsigned char pad1;
      unsigned char val;
      unsigned short pad2;
    };

    struct S1 test_and (struct S1 a, struct S2 b)
    {
      a.val &=3D b.val;

      return a;
    }

    compiles with -O2 to:

            movl    %esi, %edx
            movl    %edi, %eax
            movzbl  %dh, %esi
            andb    %sil, %al

    ANDB could use high register %dh instead of %sil:

            movl    %edi, %eax
            movl    %esi, %edx
            andb    %dh, %al

    Patch introduces strict_low_part QImode insn patterns with one of
    its input arguments extracted from high register.

            PR target/78904

    gcc/ChangeLog:

            * config/i386/i386.md (*addqi_ext<mode>_1_slp):
            New define_insn_and_split pattern.
            (*subqi_ext<mode>_1_slp): Ditto.
            (*<any_logic:code>qi_ext<mode>_1_slp): Ditto.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr78904-7.c: New test.
            * gcc.target/i386/pr78904-7a.c: New test.
            * gcc.target/i386/pr78904-7b.c: New test.=