* [Bug middle-end/80270] ICE in extract_bit_field_1 at gcc/expmed.c:1798
[not found] <bug-80270-4@http.gcc.gnu.org/bugzilla/>
@ 2021-07-24 9:17 ` pinskia at gcc dot gnu.org
2021-09-22 23:46 ` pinskia at gcc dot gnu.org
` (4 subsequent siblings)
5 siblings, 0 replies; 6+ messages in thread
From: pinskia at gcc dot gnu.org @ 2021-07-24 9:17 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80270
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords| |ice-on-valid-code
Known to fail| |12.0
Target|x86_64-*-* |x86_64-*-*, aarch64-*-*
--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Here is a testcase which is compilable on an aarch64 also:
typedef int v8 __attribute__((vector_size(8)));
struct S1 {
v8 s1f;
};
struct S2 {
struct S1 s2f1;
v8 s2f2;
};
void f(int);
#ifdef __aarch64__
#define REG "q0"
#else
#define REG "xmm0"
#endif
void fn1() {
int __trans_tmp_2, i = 3;
register struct S2 b asm(REG);
__trans_tmp_2 = b.s2f1.s1f[i];
f( __trans_tmp_2);
}
^ permalink raw reply [flat|nested] 6+ messages in thread* [Bug middle-end/80270] ICE in extract_bit_field_1 at gcc/expmed.c:1798
[not found] <bug-80270-4@http.gcc.gnu.org/bugzilla/>
2021-07-24 9:17 ` [Bug middle-end/80270] ICE in extract_bit_field_1 at gcc/expmed.c:1798 pinskia at gcc dot gnu.org
@ 2021-09-22 23:46 ` pinskia at gcc dot gnu.org
2021-09-22 23:58 ` [Bug middle-end/80270] [9/10/11/12 Regression " pinskia at gcc dot gnu.org
` (3 subsequent siblings)
5 siblings, 0 replies; 6+ messages in thread
From: pinskia at gcc dot gnu.org @ 2021-09-22 23:46 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80270
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Known to fail| |4.8.1
--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Interesting GCC 4.7's C front-end rejected this by:
<source>:20:22: error: data type of 'b' isn't suitable for a register
But the C++ front-end rejected this due to not having vector[i] being
implemented.
^ permalink raw reply [flat|nested] 6+ messages in thread* [Bug middle-end/80270] [9/10/11/12 Regression ICE in extract_bit_field_1 at gcc/expmed.c:1798
[not found] <bug-80270-4@http.gcc.gnu.org/bugzilla/>
2021-07-24 9:17 ` [Bug middle-end/80270] ICE in extract_bit_field_1 at gcc/expmed.c:1798 pinskia at gcc dot gnu.org
2021-09-22 23:46 ` pinskia at gcc dot gnu.org
@ 2021-09-22 23:58 ` pinskia at gcc dot gnu.org
2022-02-27 8:54 ` roger at nextmovesoftware dot com
` (2 subsequent siblings)
5 siblings, 0 replies; 6+ messages in thread
From: pinskia at gcc dot gnu.org @ 2021-09-22 23:58 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80270
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Summary|ICE in extract_bit_field_1 |[9/10/11/12 Regression ICE
|at gcc/expmed.c:1798 |in extract_bit_field_1 at
| |gcc/expmed.c:1798
Target Milestone|--- |9.5
See Also| |https://gcc.gnu.org/bugzill
| |a/show_bug.cgi?id=80173
Keywords|ice-on-valid-code |ice-on-invalid-code
--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Related to PR 80173. The difference between that bug and this one is simple:
b.s2f1.s1f[i];
vs
b.s2f1.s1f[3];
^ permalink raw reply [flat|nested] 6+ messages in thread* [Bug middle-end/80270] [9/10/11/12 Regression ICE in extract_bit_field_1 at gcc/expmed.c:1798
[not found] <bug-80270-4@http.gcc.gnu.org/bugzilla/>
` (2 preceding siblings ...)
2021-09-22 23:58 ` [Bug middle-end/80270] [9/10/11/12 Regression " pinskia at gcc dot gnu.org
@ 2022-02-27 8:54 ` roger at nextmovesoftware dot com
2022-02-28 22:27 ` cvs-commit at gcc dot gnu.org
2022-03-02 12:06 ` roger at nextmovesoftware dot com
5 siblings, 0 replies; 6+ messages in thread
From: roger at nextmovesoftware dot com @ 2022-02-27 8:54 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80270
Roger Sayle <roger at nextmovesoftware dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Assignee|unassigned at gcc dot gnu.org |roger at nextmovesoftware dot com
Status|NEW |ASSIGNED
Keywords|ice-on-invalid-code |ice-on-valid-code
CC| |roger at nextmovesoftware dot com
--- Comment #6 from Roger Sayle <roger at nextmovesoftware dot com> ---
Patch proposed.
https://gcc.gnu.org/pipermail/gcc-patches/2022-February/590952.html
^ permalink raw reply [flat|nested] 6+ messages in thread* [Bug middle-end/80270] [9/10/11/12 Regression ICE in extract_bit_field_1 at gcc/expmed.c:1798
[not found] <bug-80270-4@http.gcc.gnu.org/bugzilla/>
` (3 preceding siblings ...)
2022-02-27 8:54 ` roger at nextmovesoftware dot com
@ 2022-02-28 22:27 ` cvs-commit at gcc dot gnu.org
2022-03-02 12:06 ` roger at nextmovesoftware dot com
5 siblings, 0 replies; 6+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2022-02-28 22:27 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80270
--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Roger Sayle <sayle@gcc.gnu.org>:
https://gcc.gnu.org/g:7e5c6edeb1b2339e10f10bee270e61dbad985800
commit r12-7416-g7e5c6edeb1b2339e10f10bee270e61dbad985800
Author: Roger Sayle <roger@nextmovesoftware.com>
Date: Mon Feb 28 22:26:43 2022 +0000
PR middle-end/80270: ICE in extract_bit_field_1
This patch fixes PR middle-end/80270, an ICE-on-valid regression, where
performing a bitfield extraction on a variable explicitly stored in a
hard register by the user causes a segmentation fault during RTL
expansion. Nearly identical source code without the "asm" qualifier
compiles fine. The point of divergence is in simplify_gen_subreg
which tries to avoid creating non-trivial SUBREGs of hard registers,
to avoid problems during register allocation. This suggests the
simple solution proposed here, to copy hard registers to a new pseudo
in extract_integral_bit_field, just before calling simplify_gen_subreg.
2022-02-28 Roger Sayle <roger@nextmovesoftware.com>
Eric Botcazou <ebotcazou@adacore.com>
gcc/ChangeLog
PR middle-end/80270
* expmed.cc (extract_integral_bit_field): If OP0 is a hard
register, copy it to a pseudo before calling simplify_gen_subreg.
gcc/testsuite/ChangeLog
* gcc.target/i386/pr80270.c: New test case.
^ permalink raw reply [flat|nested] 6+ messages in thread* [Bug middle-end/80270] [9/10/11/12 Regression ICE in extract_bit_field_1 at gcc/expmed.c:1798
[not found] <bug-80270-4@http.gcc.gnu.org/bugzilla/>
` (4 preceding siblings ...)
2022-02-28 22:27 ` cvs-commit at gcc dot gnu.org
@ 2022-03-02 12:06 ` roger at nextmovesoftware dot com
5 siblings, 0 replies; 6+ messages in thread
From: roger at nextmovesoftware dot com @ 2022-03-02 12:06 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80270
Roger Sayle <roger at nextmovesoftware dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Target Milestone|9.5 |12.0
Status|ASSIGNED |RESOLVED
--- Comment #8 from Roger Sayle <roger at nextmovesoftware dot com> ---
This should now be fixed on mainline.
^ permalink raw reply [flat|nested] 6+ messages in thread