[Bug middle-end/80270] [9/10/11/12 Regression ICE in extract_bit_field_1 at gcc/expmed.c:1798

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80270

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Roger Sayle <sayle@gcc.gnu.org>:

https://gcc.gnu.org/g:7e5c6edeb1b2339e10f10bee270e61dbad985800

commit r12-7416-g7e5c6edeb1b2339e10f10bee270e61dbad985800
Author: Roger Sayle <roger@nextmovesoftware.com>
Date:   Mon Feb 28 22:26:43 2022 +0000

    PR middle-end/80270: ICE in extract_bit_field_1

    This patch fixes PR middle-end/80270, an ICE-on-valid regression, where
    performing a bitfield extraction on a variable explicitly stored in a
    hard register by the user causes a segmentation fault during RTL
    expansion.  Nearly identical source code without the "asm" qualifier
    compiles fine.  The point of divergence is in simplify_gen_subreg
    which tries to avoid creating non-trivial SUBREGs of hard registers,
    to avoid problems during register allocation.  This suggests the
    simple solution proposed here, to copy hard registers to a new pseudo
    in extract_integral_bit_field, just before calling simplify_gen_subreg.

    2022-02-28  Roger Sayle  <roger@nextmovesoftware.com>
                Eric Botcazou  <ebotcazou@adacore.com>

    gcc/ChangeLog
            PR middle-end/80270
            * expmed.cc (extract_integral_bit_field): If OP0 is a hard
            register, copy it to a pseudo before calling simplify_gen_subreg.

    gcc/testsuite/ChangeLog
            * gcc.target/i386/pr80270.c: New test case.