From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 7A1463858C39; Thu, 3 Nov 2022 10:04:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7A1463858C39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667469851; bh=VD5MidjOEYfzfTfU0oJKfTzueQgCZ6Is1zhYVtBHwhg=; h=From:To:Subject:Date:In-Reply-To:References:From; b=FQkuwOoAJ4WL95hXjAW2TBe8K/MAIsggVJWTRBPOjxRZbmZZp8pBZMmMJ6At1rbTr flIDdA4DxqoGcdTwFl90aVjYVkUPH1D8UobhhSU/X3Udyw9yN2vKYyl+4qpx7dDmSh EEo3YpY3hmn15qW8wRs8fHn7qn/B3mp1OJ/K2M+E= From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/80878] -mcx16 (enable 128 bit CAS) on x86_64 seems not to work on 7.1.0 Date: Thu, 03 Nov 2022 10:04:10 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 7.1.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D80878 Jakub Jelinek changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |jakub at gcc dot gnu.org --- Comment #38 from Jakub Jelinek --- Please see PR104688 . We got a response from Intel, where they guaranteed atomicity of certain 16-byte load instructions for Intel CPUs with AVX supp= ort. AFAIK we didn't get similar guarantee from AMD. The current state is that on the libatomic side when ifuncs are possible we= use those atomic loads etc. on Intel with AVX, and do what we used to do before= for other CPUs. We haven't changed what the compiler emits, I think we'd need to introduce = some new option for it (guarantee code will run only on Intel CPUs) and imply th= at from -march=3D listing Intel CPUs (with AVX). If AMD would give a similar guarantee, it would be much easier, we could just emit that whenever -mavx.=