From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 246853858D38; Thu, 3 Nov 2022 10:32:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 246853858D38 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667471530; bh=qUdO63aezliSdlKXLAqw3iSg+m1SNb+8eZyvDcTTwvc=; h=From:To:Subject:Date:In-Reply-To:References:From; b=J05bLa4obm+MUfD91jdotgFR2Lex5n5CXbunJFuKlOzEiERptGwuUIbBAse63lBOP +X4k1lEC/73S1NJVPUylDbtcU4Oq5nde9uvrsHuvNS7wdS5ZaTwulJZq+lHxKyhU7b Xl0PuGg2kckR9GuC2pZgmRPVmR2AJQ62lZXMadnU= From: "fw at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/80878] -mcx16 (enable 128 bit CAS) on x86_64 seems not to work on 7.1.0 Date: Thu, 03 Nov 2022 10:32:09 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 7.1.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: fw at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D80878 --- Comment #39 from Florian Weimer --- (In reply to Jakub Jelinek from comment #38) > Please see PR104688 . We got a response from Intel, where they guaranteed > atomicity of certain 16-byte load instructions for Intel CPUs with AVX > support. > AFAIK we didn't get similar guarantee from AMD. I'm trying to work with AMD to get an official statement that covers older = CPUs as well. I have a preliminary statement, but I hope to get to the point tha= t we can say the rule is the same as for Intel (AVX support can act as a proxy).=