[Bug rtl-optimization/83827] vector load/store with struct in registers

[Bug rtl-optimization/83827] vector load/store with struct in registers

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83827

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement

[Bug rtl-optimization/83827] vector load/store with struct in registers

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83827

--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---
For f, pass_combine failed 

Trying 20, 21 -> 22:
   20: clobber r83:TI
   21: r83:TI#0=r88:DI
      REG_DEAD r88:DI
   22: r83:TI#8=r89:DI
      REG_DEAD r89:DI
Can't combine i2 into i3

(insn 20 6 21 2 (clobber (reg/v:TI 83 [ x ])) "test.cpp":3:11 -1
     (nil))
(insn 21 20 22 2 (set (subreg:DI (reg/v:TI 83 [ x ]) 0)
        (reg:DI 88 [ x ])) "test.cpp":3:11 74 {*movdi_internal}
     (expr_list:REG_DEAD (reg:DI 88 [ x ])
        (nil)))
(insn 22 21 8 2 (set (subreg:DI (reg/v:TI 83 [ x ]) 8)
        (reg:DI 89 [+8 ])) "test.cpp":3:11 74 {*movdi_internal}
     (expr_list:REG_DEAD (reg:DI 89 [+8 ])

And it should be optimized to (set (reg:TI 83) (subreg:TI (vec_concat:V2DI
(reg:DI 88) (reg:DI 89)) 0))??

[Bug rtl-optimization/83827] vector load/store with struct in registers

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83827

--- Comment #3 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Hongtao.liu from comment #2)
> For f, pass_combine failed 
> 
Because pass_combine assmuber insn to be SET or parallel SET, but here is
CLOBBER.

  /* Can combine only if previous insn is a SET of a REG or a SUBREG,
     or a PARALLEL consisting of such a SET and CLOBBERs.

     If INSN has CLOBBER parallel parts, ignore them for our processing.
     By definition, these happen during the execution of the insn.  When it
     is merged with another insn, all bets are off.  If they are, in fact,
     needed and aren't also supplied in I3, they may be added by
     recog_for_combine.  Otherwise, it won't match.

     We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
     note.

     Get the source and destination of INSN.  If more than one, can't
     combine.  */

  if (GET_CODE (PATTERN (insn)) == SET)
    set = PATTERN (insn);
  else if (GET_CODE (PATTERN (insn)) == PARALLEL
           && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)

[Bug rtl-optimization/83827] vector load/store with struct in registers

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83827

--- Comment #4 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Hongtao.liu from comment #2)
> For f, pass_combine failed 
> 
> Trying 20, 21 -> 22:
>    20: clobber r83:TI
>    21: r83:TI#0=r88:DI
>       REG_DEAD r88:DI
>    22: r83:TI#8=r89:DI
>       REG_DEAD r89:DI
> Can't combine i2 into i3
> 
> (insn 20 6 21 2 (clobber (reg/v:TI 83 [ x ])) "test.cpp":3:11 -1
>      (nil))
Clobber was generate by simplify_gen_subreg_concatn to simplify  

(insn 4 3 5 2 (set (concatn:TI [
                (reg:DI 88)
                (reg:DI 89 [+8 ])
            ])
        (const_int 0 [0]))
"/export/users2/liuhongt/tools-build/build_intel-innersource_master_debug/test.cpp":3:11
73 {*movti_internal}
     (nil))

(insn 5 4 6 2 (set (subreg:DF (reg:TI 84) 0)
        (reg:DF 85)) "test.cpp":3:11 133 {*movdf_internal}
     (nil))
(insn 6 5 7 2 (set (subreg:DF (reg:TI 84) 8)
        (reg:DF 86)) "test.cpp":3:11 133 {*movdf_internal}
     (nil))

to

(insn 17 3 18 2 (set (reg:DI 88)
        (reg:DI 85)) "test1.cpp":3:11 74 {*movdi_internal}
     (nil))
(insn 18 17 5 2 (set (reg:DI 89 [+8 ])
        (const_int 0 [0])) "test1.cpp":3:11 74 {*movdi_internal}
     (nil))
(insn 5 18 19 2 (set (reg:DI 89 [+8 ])
        (reg:DI 86)) "test1.cpp":3:11 74 {*movdi_internal}
     (nil))
(insn 19 5 20 2 (clobber (reg/v:TI 83 [ x ])) "test1.cpp":3:11 -1
     (nil))
(insn 20 19 21 2 (set (subreg:DI (reg/v:TI 83 [ x ]) 0)
        (reg:DI 88)) "test1.cpp":3:11 74 {*movdi_internal}
     (nil))
(insn 21 20 7 2 (set (subreg:DI (reg/v:TI 83 [ x ]) 8)
        (reg:DI 89 [+8 ])) "test1.cpp":3:11 74 {*movdi_internal}
     (nil))