From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 989C93857016; Tue, 12 Oct 2021 16:21:48 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 989C93857016 From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/85730] complex code for modifying lowest byte in a 4-byte vector Date: Tue, 12 Oct 2021 16:21:47 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 9.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Oct 2021 16:21:48 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D85730 --- Comment #10 from CVS Commits --- The master branch has been updated by Uros Bizjak : https://gcc.gnu.org/g:b37351e3279d192d5d4682f002abe5b2e133bba6 commit r12-4359-gb37351e3279d192d5d4682f002abe5b2e133bba6 Author: Uros Bizjak Date: Tue Oct 12 18:20:38 2021 +0200 i386: Improve workaround for PR82524 LRA limitation [PR85730] As explained in PR82524, LRA is not able to reload strict_low_part inout operand with matched input operand. The patch introduces a workaround, where we allow LRA to generate an instruction with non-matched input operand which is split post reload to an instruction that inserts non-matched i= nput operand to an inout operand and the instruction that uses matched opera= nd. The generated code improves from: movsbl %dil, %edx movl %edi, %eax sall $3, %edx movb %dl, %al to: movl %edi, %eax movb %dil, %al salb $3, %al which is still not optimal, but the code is one instruction shorter and does not use a temporary register. 2021-10-12 Uro=C3=85=C2=A1 Bizjak gcc/ PR target/85730 PR target/82524 * config/i386/i386.md (*add_1_slp): Rewrite as define_insn_and_split pattern. Add alternative 1 and split it post reload to insert operand 1 into the low part of operand 0. (*sub_1_slp): Ditto. (*and_1_slp): Ditto. (*_1_slp): Ditto. (*ashl3_1_slp): Ditto. (*3_1_slp): Ditto. (*3_1_slp): Ditto. (*neg_1_slp): New insn_and_split pattern. (*one_cmpl_1_slp): Ditto. gcc/testsuite/ PR target/85730 PR target/82524 * gcc.target/i386/pr85730.c: New test.=