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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/86901] [AArch64] Suboptimal register allocation for int/float reinterpret
Date: Sun, 22 Aug 2021 08:37:33 +0000 [thread overview]
Message-ID: <bug-86901-4-Z2HbJNJtko@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-86901-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86901
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords|ra |
Last reconfirmed|2020-05-16 00:00:00 |2021-8-22
Component|middle-end |rtl-optimization
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The DI mode comes from combine:
Trying 7 -> 8:
7: r98:SI=r96:SF#0 0>>0x14
8: r99:SI=r98:SI&0x7ff
REG_DEAD r98:SI
Successfully matched this instruction:
(set (subreg:DI (reg:SI 99) 0)
(zero_extract:DI (subreg:DI (reg/v:SF 96 [ y ]) 0)
(const_int 11 [0xb])
(const_int 20 [0x14])))
allowing combination of insns 7 and 8
original costs 16 + 4 = 20
replacement cost 16
deferring deletion of insn with uid = 7.
modifying insn i3 8: r99:SI#0=zero_extract(r96:SF#0,0xb,0x14)
deferring rescan insn with uid = 8.
parent reply other threads:[~2021-08-22 8:37 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <bug-86901-4@http.gcc.gnu.org/bugzilla/>]
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