[Bug target/89057] [8/9/10/11 Regression] AArch64 ld3 st4 less optimized

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89057

--- Comment #10 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Sandiford <rsandifo@gcc.gnu.org>:

https://gcc.gnu.org/g:b41e6dd50f329b0291457e939d4c0dacd81c82c1

commit r11-6439-gb41e6dd50f329b0291457e939d4c0dacd81c82c1
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Mon Jan 4 11:59:07 2021 +0000

    aarch64: Improve vcombine codegen [PR89057]

    This patch fixes a codegen regression in the handling of things like:

      __temp.val[0]                                                            
 \
        = vcombine_##funcsuffix (__b.val[0],                                   
 \
                                 vcreate_##funcsuffix (__AARCH64_UINT64_C
(0))); \

    in the 64-bit vst[234] functions.  The zero was forced into a
    register at expand time, and we relied on combine to fuse the
    zero and combine back together into a single combinez pattern.
    The problem is that the zero could be hoisted before combine
    gets a chance to do its thing.

    gcc/
            PR target/89057
            * config/aarch64/aarch64-simd.md (aarch64_combine<mode>): Accept
            aarch64_simd_reg_or_zero for operand 2.  Use the combinez patterns
            to handle zero operands.

    gcc/testsuite/
            PR target/89057
            * gcc.target/aarch64/pr89057.c: New test.