From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id CE0AA385DDC1; Wed, 18 Sep 2024 01:06:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CE0AA385DDC1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1726621570; bh=WO0Fn7HiKGohQ4SnDJ/HgzcVLi3MRHgOJrjdSIg68yQ=; h=From:To:Subject:Date:In-Reply-To:References:From; b=V389EtG2e0gz3dET6bV89FMZcBOUUz6IfgGcV6SK6JaK8RnsfTB7rZbjXzT2oGBON edzSJHMf79+ZUS4L7WvlCghiPSb49NnWF8jUJkYlFZ+dYEZ+2AQAFQaGhVfgeoKOLq o16Me561Nm4IJHIIidV3sjIvMAY8f8OCFvNElF0U= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/89213] Optimize V2DI shifts by a constant on power8 & above systems. Date: Wed, 18 Sep 2024 01:06:06 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 9.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: meissner at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D89213 --- Comment #9 from GCC Commits --- The master branch has been updated by Michael Meissner : https://gcc.gnu.org/g:9a07ac151327f61963b092062eb8566dd0c6f0cd commit r15-3676-g9a07ac151327f61963b092062eb8566dd0c6f0cd Author: Michael Meissner Date: Tue Sep 17 21:05:27 2024 -0400 PR 89213: Add better support for shifting vectors with 64-bit elements This patch fixes PR target/89213 to allow better code to be generated t= o do constant shifts of V2DI/V2DF vectors. Previously GCC would do constant shifts of vectors with 64-bit elements by using: XXSPLTIB 32,4 VEXTSB2D 0,0 VSRAD 2,2,0 I.e., the PowerPC does not have a VSPLTISD instruction to load -15..14 = for the 64-bit shift count in one instruction. Instead, it would need to load a byte and then convert it to 64-bit. With this patch, GCC now realizes that the vector shift instructions wi= ll look at the bottom 6 bits for the shift count, and it can use either a VSPLT= ISW or XXSPLTIB instruction to load the shift count. 2024-09-17 Michael Meissner gcc/ PR target/89213 * config/rs6000/altivec.md (UNSPEC_VECTOR_SHIFT): New unspec. (VSHIFT_MODE): New mode iterator. (vshift_code): New code iterator. (vshift_attr): New code attribute. (altivec___const): New pattern to optimize vector long long/int shifts by a constant. (altivec__shift_const): New helper insn to load up a constant used by the shift operation. * config/rs6000/predicates.md (vector_shift_constant): New predicate. gcc/testsuite/ PR target/89213 * gcc.target/powerpc/pr89213.c: New test. * gcc.target/powerpc/vec-rlmi-rlnm.c: Update instruction count.=