[Bug rtl-optimization/89310] Poor code generation returning float field from a struct

[Bug rtl-optimization/89310] Poor code generation returning float field from a struct

[luoxhu at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89310

luoxhu at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |luoxhu at gcc dot gnu.org

--- Comment #3 from luoxhu at gcc dot gnu.org ---
rs6000.md:

(define_insn_and_split "movsf_from_si"
...
  "&& reload_completed
   && vsx_reg_sfsubreg_ok (operands[0], SFmode)
   && int_reg_operand_not_pseudo (operands[1], SImode)"
  [(const_int 0)
...
  /* Move SF value to upper 32-bits for xscvspdpn.  */
  emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
  emit_insn (gen_p8_mtvsrd_sf (op0, op2));
  emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
  DONE


The split seems inevitable as reload_completed is true here, can this
lshrdi3+ashldi3 be optimized by peephole? 

r9 is DImode, is there any benefit of using mtvsrw[az] instead of mtvsrd?

Or could we replace the 3 instructions with better sequence?  Thanks.

[Bug rtl-optimization/89310] Poor code generation returning float field from a struct

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89310

--- Comment #4 from Segher Boessenkool <segher at gcc dot gnu.org> ---
Maybe you can make a define_insn_and_split for the lshrdi3 plus this?
Which will split to an insn fewer immediately.

If you split after reload you need many extra patterns to get the most
basic optimisations done for its result...  But (at least in this case)
you do not need a peephole at least ;-)

[Bug rtl-optimization/89310] Poor code generation returning float field from a struct

[luoxhu at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89310

--- Comment #5 from luoxhu at gcc dot gnu.org ---
Thanks.  I copied the code from movsf_from_si to make a define_insn_and_split
for "movsf_from_si2", but we don't have define_insn for rldicr, so I use
gen_anddi3 instead, any comment?

foo:
.LFB0:
        .cfi_startproc
        rldicr 3,3,0,31
        mtvsrd 1,3
        xscvspdpn 1,1
        blr


diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4fcd6a94022..92c237edfad 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7593,6 +7593,48 @@ (define_insn_and_split "movsf_from_si"
            "*,          *,         p9v,       p8v,       *,         *,
             p8v,        p8v,       p8v,       *")])

+(define_insn_and_split "movsf_from_si2"
+  [(set (match_operand:SF 0 "nonimmediate_operand"
+           "=!r,       f,         v,         wa,        m,         Z,
+            Z,         wa,        ?r,        !r")
+           (unspec:SF [
+            (subreg:SI (ashiftrt:DI
+              (match_operand:DI 1 "input_operand"
+          "m,         m,         wY,        Z,         r,         f,
+          wa,        r,         wa,        r")
+         (const_int 32)) 0)]
+                  UNSPEC_SF_FROM_SI))
+   (clobber (match_scratch:DI 2
+           "=X,        X,         X,         X,         X,         X,
+             X,         r,         X,         X"))]
+  "TARGET_NO_SF_SUBREG
+   && (register_operand (operands[0], SFmode)
+       || register_operand (operands[1], SImode))"
+   "#"
+  "&& !reload_completed
+   && vsx_reg_sfsubreg_ok (operands[0], SFmode)"
+  [(const_int 0)]
+{
+  rtx op0 = operands[0];
+  rtx op1 = operands[1];
+  rtx tmp = gen_reg_rtx (DImode);
+
+  emit_insn (gen_anddi3 (tmp, op1, GEN_INT(0xFFFFFFFF00000000ULL)));
+  emit_insn (gen_p8_mtvsrd_sf (op0, tmp));
+  emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
+  DONE;
+})
+

[Bug rtl-optimization/89310] Poor code generation returning float field from a struct

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89310

--- Comment #6 from Segher Boessenkool <segher at gcc dot gnu.org> ---
rldicr is one of the insns generated by "*rotl<mode>3_mask", which
recognises all canonical formulations of all our rotate-and-mask
instructions.

[Bug rtl-optimization/89310] Poor code generation returning float field from a struct

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89310

--- Comment #7 from luoxhu at gcc dot gnu.org ---
(In reply to Segher Boessenkool from comment #6)
> rldicr is one of the insns generated by "*rotl<mode>3_mask", which
> recognises all canonical formulations of all our rotate-and-mask
> instructions.

Yes, rldicr could also be generated by "and<mode>3_mask", for this case, I
suppose use and_di3_mask without shift right and left is enough? (Below is
minor change with hard code 0xFFFFFFFF00000000ULL replaced.)


   rtx mask = GEN_INT (HOST_WIDE_INT_M1U << 32);
   emit_insn (gen_anddi3 (tmp, op1, mask));
   emit_insn (gen_p8_mtvsrd_sf (op0, tmp));
   emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
   DONE;

--- Comment #8 from Segher Boessenkool <segher at gcc dot gnu.org> ---
That looks good yes.

[Bug rtl-optimization/89310] Poor code generation returning float field from a struct

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89310

--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Xiong Hu Luo <luoxhu@gcc.gnu.org>:

https://gcc.gnu.org/g:2ef4cf87a7c7f36c1fe523e4d71bbb4846ab0c35

commit r11-2245-g2ef4cf87a7c7f36c1fe523e4d71bbb4846ab0c35
Author: Xionghu Luo <luoxhu@linux.ibm.com>
Date:   Mon Jul 20 22:37:30 2020 -0500

    rs6000: Define movsf_from_si2 to extract high part SF element from
DImode[PR89310]

    For extracting high part element from DImode register like:

    {%1:SF=unspec[r122:DI>>0x20#0] 86;clobber scratch;}

    split it before reload with "and mask" to avoid generating shift right
    32 bit then shift left 32 bit.  This pattern also exists in PR42475 and
    PR67741, etc.

    srdi 3,3,32
    sldi 9,3,32
    mtvsrd 1,9
    xscvspdpn 1,1

    =>

    rldicr 3,3,0,31
    mtvsrd 1,3
    xscvspdpn 1,1

    Bootstrap and regression tested pass on Power8-LE.

    gcc/ChangeLog:

    2020-07-21  Xionghu Luo  <luoxhu@linux.ibm.com>

            PR rtl-optimization/89310
            * config/rs6000/rs6000.md (movsf_from_si2): New
define_insn_and_split.

    gcc/testsuite/ChangeLog:

    2020-07-21  Xionghu Luo  <luoxhu@linux.ibm.com>

            PR rtl-optimization/89310
            * gcc.target/powerpc/pr89310.c: New test.

[Bug rtl-optimization/89310] Poor code generation returning float field from a struct

[luoxhu at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89310

luoxhu at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #10 from luoxhu at gcc dot gnu.org ---
Fixed on upstream.