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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/89310] Poor code generation returning float
 field from a struct
Date: Tue, 21 Jul 2020 03:37:57 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D89310

--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Xiong Hu Luo <luoxhu@gcc.gnu.org>:

https://gcc.gnu.org/g:2ef4cf87a7c7f36c1fe523e4d71bbb4846ab0c35

commit r11-2245-g2ef4cf87a7c7f36c1fe523e4d71bbb4846ab0c35
Author: Xionghu Luo <luoxhu@linux.ibm.com>
Date:   Mon Jul 20 22:37:30 2020 -0500

    rs6000: Define movsf_from_si2 to extract high part SF element from
DImode[PR89310]

    For extracting high part element from DImode register like:

    {%1:SF=3Dunspec[r122:DI>>0x20#0] 86;clobber scratch;}

    split it before reload with "and mask" to avoid generating shift right
    32 bit then shift left 32 bit.  This pattern also exists in PR42475 and
    PR67741, etc.

    srdi 3,3,32
    sldi 9,3,32
    mtvsrd 1,9
    xscvspdpn 1,1

    =3D>

    rldicr 3,3,0,31
    mtvsrd 1,3
    xscvspdpn 1,1

    Bootstrap and regression tested pass on Power8-LE.

    gcc/ChangeLog:

    2020-07-21  Xionghu Luo  <luoxhu@linux.ibm.com>

            PR rtl-optimization/89310
            * config/rs6000/rs6000.md (movsf_from_si2): New
define_insn_and_split.

    gcc/testsuite/ChangeLog:

    2020-07-21  Xionghu Luo  <luoxhu@linux.ibm.com>

            PR rtl-optimization/89310
            * gcc.target/powerpc/pr89310.c: New test.=