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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/89984] Extra register move
Date: Wed, 01 Sep 2021 08:42:13 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D89984

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2021-09-01
           Keywords|                            |easyhack
     Ever confirmed|0                           |1
          Component|rtl-optimization            |target

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The problem is here:
(define_insn_and_split "@xorsign<mode>3_1"
  [(set (match_operand:MODEF 0 "register_operand" "=3DYv")
        (unspec:MODEF
          [(match_operand:MODEF 1 "register_operand" "Yv")
           (match_operand:MODEF 2 "register_operand" "0")
           (match_operand:<ssevecmode> 3 "nonimmediate_operand" "Yvm")]
          UNSPEC_XORSIGN))]
  "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
  "#"
  "&& reload_completed"
  [(const_int 0)]
  "ix86_split_xorsign (operands); DONE;")


for AVX operand 2 does not need to be the same as operand 0.
Shouldn't be a hard change for someone starting out to improve this.=