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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/91681] Missed optimization for 128 bit arithmetic
 operations
Date: Wed, 12 Jul 2023 13:14:57 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D91681

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Roger Sayle <sayle@gcc.gnu.org>:

https://gcc.gnu.org/g:275a2124e4928c88bd5469096356ba393b6aadfb

commit r14-2466-g275a2124e4928c88bd5469096356ba393b6aadfb
Author: Roger Sayle <roger@nextmovesoftware.com>
Date:   Wed Jul 12 14:14:15 2023 +0100

    i386: Fix FAIL of gcc.target/i386/pr91681-1.c

    The recent change in TImode parameter passing on x86_64 results in the
    FAIL of pr91681-1.c.  The issue is that with the extra flexibility,
    the combine pass is now spoilt for choice between using either the
    *add<dwi>3_doubleword_concat or the *add<dwi>3_doubleword_zext
    patterns, when one operand is a *concat and the other is a zero_extend.
    The solution proposed below is provide an *add<dwi>3_doubleword_concat_=
zext
    define_insn_and_split, that can benefit both from the register allocati=
on
    of *concat, and still avoid the xor normally required by zero extension.

    I'm investigating a follow-up refinement to improve register allocation
    further by avoiding the early clobber in the =3D&r, and handling (custo=
m)
    reloads explicitly, but this piece resolves the testcase failure.

    2023-07-12  Roger Sayle  <roger@nextmovesoftware.com>

    gcc/ChangeLog
            PR target/91681
            * config/i386/i386.md (*add<dwi>3_doubleword_concat_zext): New
            define_insn_and_split derived from *add<dwi>3_doubleword_concat
            and *add<dwi>3_doubleword_zext.=