From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id E68FC385842B; Tue, 20 Jun 2023 19:37:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E68FC385842B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1687289866; bh=fWRKG3wgHWxgqezXEyO86f5XS9XYKstZDOm7ldHiNGw=; h=From:To:Subject:Date:In-Reply-To:References:From; b=OlhaHtZI+hcYvRPczADKtMu2V+/90Cvv6M97eXoyY7fKOGLPiNLhL8VGXvKCrbQug UfYi4BslHmvxMgDj7SXiBHlkbXNp2p5LXOjkPT9xslpOnLlbk6ketGW+o6b5vUxKuh qnjQT6L9JGrEw036GpkAGpYNbzNswUYZRKmZDTpY= From: "bergner at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/91804] [10/11/12/13/14 regression] r265398 breaks gcc.target/powerpc/vec-rlmi-rlnm.c Date: Tue, 20 Jun 2023 19:37:46 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 10.0 X-Bugzilla-Keywords: missed-optimization, ra X-Bugzilla-Severity: normal X-Bugzilla-Who: bergner at gcc dot gnu.org X-Bugzilla-Status: RESOLVED X-Bugzilla-Resolution: FIXED X-Bugzilla-Priority: P4 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 10.5 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_status cc resolution Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D91804 Peter Bergner changed: What |Removed |Added ---------------------------------------------------------------------------- Status|NEW |RESOLVED CC| |pthaugen at gcc dot gnu.org Resolution|--- |FIXED --- Comment #9 from Peter Bergner --- (In reply to Ajit Kumar Agarwal from comment #8) > I don't see extra xxlor with latest gcc trunk. I think this is fixed. > I think we should close this PR. Thanks for looking Ajit. I did a git bisect and it flagged a patch from Pa= t as fixing this: commit 51d89e61f7ebfe75ca752e62bd29b58cb957235c Author: Pat Haugen AuthorDate: Mon May 10 13:49:06 2021 -0500 Commit: Pat Haugen CommitDate: Mon May 10 13:49:06 2021 -0500 Add ALTIVEC_REGS as pressure class. Code that has heavy register pressure on Altivec registers can suffer f= rom over-aggressive scheduling during sched1, which then leads to increased register spill. This is due to the fact that registers that prefer ALTIVEC_REGS are currently assigned an allocno class of VSX_REGS. This = then misleads the scheduler to think there are 64 regs available, when in reality there are only 32 Altivec regs. This patch fixes the problem by assigni= ng an allocno class of ALTIVEC_REGS and adding ALTIVEC_REGS as a pressure cla= ss. 2021-05-10 Pat Haugen gcc/ChangeLog: * config/rs6000/rs6000.c (rs6000_ira_change_pseudo_allocno_clas= s): Return ALTIVEC_REGS if that is best_class. (rs6000_compute_pressure_classes): Add ALTIVEC_REGS. gcc/testsuite/ChangeLog: * gcc.target/powerpc/fold-vec-insert-float-p9.c: Adjust counts. * gcc.target/powerpc/vec-rlmi-rlnm.c: Likewise.=