From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id CEC343858C36; Thu, 27 Jul 2023 11:11:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CEC343858C36 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1690456316; bh=hp4oqz8vCZHpU6Q8pKykK7Yyf2jfvgXKFea78f27ggc=; h=From:To:Subject:Date:In-Reply-To:References:From; b=ZRLtQqaO9UWjn3Pd4UlTMumCRwWKXmT6Cl6W2fmuEn5QNI6CntieY8CQWnOP1Wa1h 86nQpHE2TAxfl16PIu7b6rL/19S29FCSAip8ma87N5jRL2uFEdLrUTThwgSd1qKeAS whVan1ZKAbhQIDzc8PdZjxibblMKSwhN+qyTSgSQ= From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/91838] [8/9 Regression] incorrect use of shr and shrx to shift by 64, missed optimization of vector shift Date: Thu, 27 Jul 2023 11:11:54 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 9.2.0 X-Bugzilla-Keywords: missed-optimization, wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: REOPENED X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: tnfchris at gcc dot gnu.org X-Bugzilla-Target-Milestone: 8.4 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D91838 --- Comment #17 from Richard Biener --- Interestingly even with -mno-sse we somehow have a shift for V2QImode. When a scalar shift by precision is in the IL (for example via veclower) then it's CCPs bit value tracking that makes it zero, if that's disabled then VRP will compute it zero. But we don't have any pattern that would consistently do this. I'm going to add one.=