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* [Bug target/91913] [8/9 Regression] ICE in extract_constrain_insn, at recog.c:2211
[not found] <bug-91913-4@http.gcc.gnu.org/bugzilla/>
@ 2020-03-12 15:13 ` rearnsha at gcc dot gnu.org
2020-03-12 18:46 ` marxin at gcc dot gnu.org
2020-03-12 18:47 ` marxin at gcc dot gnu.org
2 siblings, 0 replies; 3+ messages in thread
From: rearnsha at gcc dot gnu.org @ 2020-03-12 15:13 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91913
Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|ASSIGNED |RESOLVED
--- Comment #12 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Fixed on gcc-9 with
https://gcc.gnu.org/pipermail/gcc-cvs/2020-March/271649.html
(https://gcc.gnu.org/g:08f00a213f8a1b99bbf3ad3c337dea249a288cf1)
Fixed on gcc-8 with
https://gcc.gnu.org/pipermail/gcc-cvs/2020-March/271650.html
(https://gcc.gnu.org/g:3d46f4875c6c50e8095294b6b700d6678a7e2f1e)
^ permalink raw reply [flat|nested] 3+ messages in thread* [Bug target/91913] [8/9 Regression] ICE in extract_constrain_insn, at recog.c:2211
[not found] <bug-91913-4@http.gcc.gnu.org/bugzilla/>
2020-03-12 15:13 ` [Bug target/91913] [8/9 Regression] ICE in extract_constrain_insn, at recog.c:2211 rearnsha at gcc dot gnu.org
@ 2020-03-12 18:46 ` marxin at gcc dot gnu.org
2020-03-12 18:47 ` marxin at gcc dot gnu.org
2 siblings, 0 replies; 3+ messages in thread
From: marxin at gcc dot gnu.org @ 2020-03-12 18:46 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91913
--- Comment #13 from Martin Liška <marxin at gcc dot gnu.org> ---
commit r8-10119-g3d46f4875c6c50e8095294b6b700d6678a7e2f1e
Author: Richard Earnshaw <rearnsha@arm.com>
Date: Fri Mar 6 10:04:51 2020 +0000
arm: correct constraints on movsi_compare0 [PR91913]
The peephole that detects a mov of one register to another followed by
a comparison of the original register against zero is only used in Arm
state; but the instruction that matches this is generic to all 32-bit
compilation states. That instruction lacks support for SP which is
permitted in Arm state, but has restrictions in Thumb2 code.
This patch fixes the problem by allowing SP when in ARM state for all
registers; in Thumb state it allows SP only as a source when the
register really is copied to another target.
gcc/ChangeLog:
PR target/91913
Backport from master
* config/arm/arm.md (movsi_compare0): Allow SP as a source register
in Thumb state and also as a destination in Arm state. Add T16
variants.
gcc/testsuite/ChangeLog:
2020-02-10 Jakub Jelinek <jakub@redhat.com>
PR target/91913
Backport from master
* gfortran.dg/pr91913.f90: New test.
^ permalink raw reply [flat|nested] 3+ messages in thread* [Bug target/91913] [8/9 Regression] ICE in extract_constrain_insn, at recog.c:2211
[not found] <bug-91913-4@http.gcc.gnu.org/bugzilla/>
2020-03-12 15:13 ` [Bug target/91913] [8/9 Regression] ICE in extract_constrain_insn, at recog.c:2211 rearnsha at gcc dot gnu.org
2020-03-12 18:46 ` marxin at gcc dot gnu.org
@ 2020-03-12 18:47 ` marxin at gcc dot gnu.org
2 siblings, 0 replies; 3+ messages in thread
From: marxin at gcc dot gnu.org @ 2020-03-12 18:47 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91913
--- Comment #14 from Martin Liška <marxin at gcc dot gnu.org> ---
commit r9-8364-g08f00a213f8a1b99bbf3ad3c337dea249a288cf1
Author: Richard Earnshaw <rearnsha@arm.com>
Date: Fri Mar 6 10:04:51 2020 +0000
arm: correct constraints on movsi_compare0 [PR91913]
The peephole that detects a mov of one register to another followed by
a comparison of the original register against zero is only used in Arm
state; but the instruction that matches this is generic to all 32-bit
compilation states. That instruction lacks support for SP which is
permitted in Arm state, but has restrictions in Thumb2 code.
This patch fixes the problem by allowing SP when in ARM state for all
registers; in Thumb state it allows SP only as a source when the
register really is copied to another target.
gcc/ChangeLog:
PR target/91913
Backport from master
* config/arm/arm.md (movsi_compare0): Allow SP as a source register
in Thumb state and also as a destination in Arm state. Add T16
variants.
gcc/testsuite/ChangeLog:
2020-02-10 Jakub Jelinek <jakub@redhat.com>
PR target/91913
Backport from master
* gfortran.dg/pr91913.f90: New test.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2020-03-12 15:13 ` [Bug target/91913] [8/9 Regression] ICE in extract_constrain_insn, at recog.c:2211 rearnsha at gcc dot gnu.org
2020-03-12 18:46 ` marxin at gcc dot gnu.org
2020-03-12 18:47 ` marxin at gcc dot gnu.org
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