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From: "marxin at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/91913] [8/9 Regression] ICE in extract_constrain_insn,
 at recog.c:2211
Date: Thu, 12 Mar 2020 18:46:45 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D91913

--- Comment #13 from Martin Li=C5=A1ka <marxin at gcc dot gnu.org> ---
commit r8-10119-g3d46f4875c6c50e8095294b6b700d6678a7e2f1e
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Fri Mar 6 10:04:51 2020 +0000

    arm: correct constraints on movsi_compare0 [PR91913]

    The peephole that detects a mov of one register to another followed by
    a comparison of the original register against zero is only used in Arm
    state; but the instruction that matches this is generic to all 32-bit
    compilation states.  That instruction lacks support for SP which is
    permitted in Arm state, but has restrictions in Thumb2 code.

    This patch fixes the problem by allowing SP when in ARM state for all
    registers; in Thumb state it allows SP only as a source when the
    register really is copied to another target.

    gcc/ChangeLog:
            PR target/91913
            Backport from master
            * config/arm/arm.md (movsi_compare0): Allow SP as a source regi=
ster
            in Thumb state and also as a destination in Arm state.  Add T16
            variants.

    gcc/testsuite/ChangeLog:
            2020-02-10  Jakub Jelinek  <jakub@redhat.com>

            PR target/91913
            Backport from master
            * gfortran.dg/pr91913.f90: New test.=