[Bug target/94052] Paradoxical subregs out of expand causes ICE with multi register modes at -O2 or higher

[Bug target/94052] Paradoxical subregs out of expand causes ICE with multi register modes at -O2 or higher

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94052

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Sandiford <rsandifo@gcc.gnu.org>:

https://gcc.gnu.org/g:497498c878d48754318e486428e2aa30854020b9

commit r10-7312-g497498c878d48754318e486428e2aa30854020b9
Author: Richard Sandiford <richard.sandiford@arm.com>
Date:   Mon Mar 9 19:42:57 2020 +0000

    lra: Tighten check for reloading paradoxical subregs [PR94052]

    simplify_operand_subreg tries to detect whether the allocation for
    a pseudo in a paradoxical subreg is also valid for the outer mode.
    The condition it used to check for an invalid combination was:

      else if (REG_P (reg)
               && REGNO (reg) >= FIRST_PSEUDO_REGISTER
               && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0
               && (hard_regno_nregs (hard_regno, innermode)
                   < hard_regno_nregs (hard_regno, mode))
               && (regclass = lra_get_allocno_class (REGNO (reg)))
               && (type != OP_IN
                   || !in_hard_reg_set_p (reg_class_contents[regclass],
                                          mode, hard_regno)
                   || overlaps_hard_reg_set_p (lra_no_alloc_regs,
                                               mode, hard_regno)))

    I think there are two problems with this:

    (1) It never actually checks whether the hard register is valid for the
        outer mode (in the hard_regno_mode_ok sense).  If it isn't, any attempt
        to reload in the outer mode is likely to cycle, because the implied
        regno/mode combination will be just as invalid next time
        curr_insn_transform sees the subreg.

    (2) The check is valid for little-endian only.  For big-endian we need
        to move hard_regno backwards.

    Using simplify_subreg_regno should avoid both problems.

    As the existing comment says, IRA should always take subreg references
    into account when allocating hard registers, so this fix-up should only
    really be needed for pseudos allocated by LRA itself.

    gcc/
    2020-03-21  Richard Sandiford  <richard.sandiford@arm.com>

            PR rtl-optimization/94052
            * lra-constraints.c (simplify_operand_subreg): Reload the inner
            register of a paradoxical subreg if simplify_subreg_regno fails
            to give a valid hard register for the outer mode.

    gcc/testsuite/
    2020-03-21  Tamar Christina  <tamar.christina@arm.com>

            PR target/94052
            * gcc.target/aarch64/pr94052.C: New test.

[Bug target/94052] Paradoxical subregs out of expand causes ICE with multi register modes at -O2 or higher

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94052

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Tamar Christina
<tnfchris@gcc.gnu.org>:

https://gcc.gnu.org/g:8fa2081ca6288853f3b8ceecd7d57ddf5dba5e7a

commit r9-8412-g8fa2081ca6288853f3b8ceecd7d57ddf5dba5e7a
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Tue Mar 24 12:36:19 2020 +0000

    AArch64: Break apart paradoxical subregs for VSTRUCT writes (PR
target/94052)

    This works around an ICE in reload where from expand we get the following
RTL
    generated for VSTRUCT mode writes:

    (insn 446 354 445 2 (set (reg:CI 383)
     (subreg:CI (reg:V4SI 291) 0)) "small.i":146:22 3408 {*aarch64_movci}
     (nil))

    This sequence is trying to say two things:

    1) liveliness: It's trying to say that eventually the whole CI reg will be
                   written to. It does this by generating the paradoxical
subreg.
    2) write data: It's trying to in the same instruction also write the V4SI
mode
                   component at offset 0 in the CI reg.

    This patch fixes it by in the backend when we see such a paradoxical
    construction breaking it apart and issuing a clobber to correct the
liveliness
    information and then emitting a normal subreg write for the component that
the
    paradoxical subreg was trying to write to.

    Concretely we generate this:

    (insn 42 41 43 (clobber (reg/v:CI 122 [ diD.5226 ])) "small.i":121:23 -1
         (nil))

    (insn 43 42 44 (set (subreg:V4SI (reg/v:CI 122 [ diD.5226 ]) 0)
            (reg:V4SI 136)) "small.i":121:23 -1
         (nil))

    gcc/ChangeLog:

            PR target/94052
            * config/aarch64/aarch64-simd.md (mov<mode>): Remove paradoxical
            subregs of VSTRUCT modes.

    gcc/testsuite/ChangeLog:

            PR target/94052
            * g++.target/aarch64/pr94052.C: New test.

[Bug target/94052] Paradoxical subregs out of expand causes ICE with multi register modes at -O2 or higher

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94052

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Tamar Christina
<tnfchris@gcc.gnu.org>:

https://gcc.gnu.org/g:0349bc70454e4de18d1cdf5eea0917646fdf79ae

commit r8-10139-g0349bc70454e4de18d1cdf5eea0917646fdf79ae
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Tue Mar 24 15:00:44 2020 +0000

    AArch64: Break apart paradoxical subregs for VSTRUCT writes (PR
target/94052)

    This works around an ICE in reload where from expand we get the following
RTL
    generated for VSTRUCT mode writes:

    (insn 446 354 445 2 (set (reg:CI 383)
     (subreg:CI (reg:V4SI 291) 0)) "small.i":146:22 3408 {*aarch64_movci}
     (nil))

    This sequence is trying to say two things:

    1) liveliness: It's trying to say that eventually the whole CI reg will be
                   written to. It does this by generating the paradoxical
subreg.
    2) write data: It's trying to in the same instruction also write the V4SI
mode
                   component at offset 0 in the CI reg.

    This patch fixes it by in the backend when we see such a paradoxical
    construction breaking it apart and issuing a clobber to correct the
liveliness
    information and then emitting a normal subreg write for the component that
the
    paradoxical subreg was trying to write to.

    Concretely we generate this:

    (insn 42 41 43 (clobber (reg/v:CI 122 [ diD.5226 ])) "small.i":121:23 -1
         (nil))

    (insn 43 42 44 (set (subreg:V4SI (reg/v:CI 122 [ diD.5226 ]) 0)
            (reg:V4SI 136)) "small.i":121:23 -1
         (nil))

    gcc/ChangeLog:

            PR target/94052
            * config/aarch64/aarch64-simd.md (mov<mode>): Remove paradoxical
            subregs of VSTRUCT modes.

    gcc/testsuite/ChangeLog:

            * g++.target/aarch64/aarch64.exp: New file.
            * g++.target/aarch64/pr94052.C: New test.

[Bug target/94052] Paradoxical subregs out of expand causes ICE with multi register modes at -O2 or higher

[tnfchris at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94052

Tamar Christina <tnfchris at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #9 from Tamar Christina <tnfchris at gcc dot gnu.org> ---
Issue fixed in GCC 10 and backported to GCC 8 and 9.