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From: "ams at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/94248] [amdgcn] Doesn't build with RTL checking
Date: Tue, 21 Apr 2020 13:14:22 +0000 [thread overview]
Message-ID: <bug-94248-4-UTXMDhcHoL@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-94248-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94248
--- Comment #5 from Andrew Stubbs <ams at gcc dot gnu.org> ---
(In reply to Thomas Schwinge from comment #4)
> (In reply to Andrew Stubbs from comment #3)
> > Actually, I think that recent changes to the register alignment mean that
> > this can't happen any more, so the whole check is probably obsolete.
>
> I don't know exactly what "this" and "the whole check" relate to, but I do
> reconfirm that without Jakub's 'reg_overlap_mentioned_p' patch, I'm still
> running into the ICE.
I meant that I don't believe that overlapping registers can happen, thus the
condition will always be false.
Yes, the REG_P can still ICE with the additional checking enabled.
next prev parent reply other threads:[~2020-04-21 13:14 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-21 11:27 [Bug target/94248] New: " tschwinge at gcc dot gnu.org
2020-03-21 14:39 ` [Bug target/94248] " jakub at gcc dot gnu.org
2020-03-23 10:43 ` tschwinge at gcc dot gnu.org
2020-03-23 10:49 ` ams at gcc dot gnu.org
2020-04-21 12:59 ` tschwinge at gcc dot gnu.org
2020-04-21 13:14 ` ams at gcc dot gnu.org [this message]
2020-04-22 9:47 ` tschwinge at gcc dot gnu.org
2020-04-22 12:10 ` ams at gcc dot gnu.org
2020-04-29 7:58 ` cvs-commit at gcc dot gnu.org
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