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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/94343] [10 Regression] invalid AVX512VL vpternlogd
 instruction emitted for -march=knl
Date: Thu, 26 Mar 2020 16:41:11 +0000
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X-Bugzilla-Keywords: missed-optimization, wrong-code
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94343

--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I was thinking about
--- gcc/config/i386/sse.md.jj   2020-03-06 11:35:46.284074858 +0100
+++ gcc/config/i386/sse.md      2020-03-26 17:35:23.690515228 +0100
@@ -12800,10 +12800,18 @@
        (xor:VI (match_operand:VI 1 "nonimmediate_operand" "vm")
                (match_operand:VI 2 "vector_all_ones_operand" "BC")))]
   "TARGET_AVX512F"
-  "vpternlog<ternlogsuffix>\t{$0x55, %1, %0,
%0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}"
+{
+  if (TARGET_AVX512VL)
+    return "vpternlog<ternlogsuffix>\t{$0x55, %1, %0,
%0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}";
+  else
+    return "vpternlog<ternlogsuffix>\t{$0x55, %g1, %g0,
%g0<mask_operand3>|%g0<mask_operand3>, %g0, %g1, 0x55}";
+}
   [(set_attr "type" "sselog")
    (set_attr "prefix" "evex")
-   (set_attr "mode" "<sseinsnmode>")])
+   (set (attr "mode")
+        (if_then_else (match_test "TARGET_AVX512VL")
+                     (const_string "<sseinsnmode>")
+                     (const_string "XI")))])

 (define_expand "<sse2_avx2>_andnot<mode>3"
   [(set (match_operand:VI_AVX2 0 "register_operand")
instead.  I'm aware that from performance POV we are trying to avoid 512-bit
vectors, but don't all such affected CPUs support AVX512VL already?  Does K=
NL
care if it will do a 512-bit operation instead of 128-bit or 256-bit?=