From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id B504A385E014; Fri, 27 Mar 2020 07:31:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B504A385E014 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1585294319; bh=Eg7Go4etxAePrWuMb31+k0xafZLJ2ejWB65AK3ecaVY=; h=From:To:Subject:Date:In-Reply-To:References:From; b=mQDXMCoCvKeIX+XjYPMV1Kq5HOVsn7BRM9hQGUfgaWMlIkwb8wYbUsdpc+sQ4GPcA dALo4s91mZYwB+lbYq2qMcvpLqIGh8hYj7hv7IG3UCLEmZpi4ZXEJloaNbpirn9SEs DNveyLN91zEQ8JOYHy49LPXkhF/LkrwAfWJ3T+ig= From: "jbeulich at suse dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/94343] [10 Regression] invalid AVX512VL vpternlogd instruction emitted for -march=knl Date: Fri, 27 Mar 2020 07:31:59 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 10.0 X-Bugzilla-Keywords: missed-optimization, wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: jbeulich at suse dot com X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P1 X-Bugzilla-Assigned-To: jakub at gcc dot gnu.org X-Bugzilla-Target-Milestone: 10.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Mar 2020 07:31:59 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94343 --- Comment #13 from jbeulich at suse dot com --- As to using 512-bit operations even on more narrow input types - is this correct when e.g. subsequently source code upcasts the vector? I.e. would s= uch an upcast be carried out by emitting an insn to zero the upper portion, rat= her than simply considering this a re-interpretation of the same register (with= no insn emitted at all)? In which case the fix would apparently boil down to u= sing a mode iterator different from VI (VI48_AVX512VL if you really mean to excl= ude vectors of QI/HI, or a combination of this and VI12_AVX512VL otherwise).=