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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/94435] [9/10 Regression] ICE in extract_insn, at
 recog.c:2294
Date: Wed, 22 Apr 2020 16:10:06 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94435

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-8 branch has been updated by Andre Simoes Dias Vieira
<avieira@gcc.gnu.org>:

https://gcc.gnu.org/g:1dbd821ee74e6c234e61e25b0801a0b0949bcc67

commit r8-10214-g1dbd821ee74e6c234e61e25b0801a0b0949bcc67
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu Apr 16 10:16:18 2020 +0100

    aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435]

    The following testcase ICEs, because aarch64_gen_compare_reg_maybe_ze e=
mits
    invalid RTL.
    For y_mode [QH]Imode it expects y to be of that mode (or CONST_INT that
fits
    into that mode) and x being SImode; for non-CONST_INT y it zero extends=
 y
    into SImode and compares that against x, for CONST_INT y it zero extend=
s y
    into SImode.  The problem is that when the zero extended constant isn't
    usable directly, it forces it into a REG, but with y_mode mode, and then
    compares against y.  That is wrong, because it should force it into a
SImode
    REG and compare that way.

    2020-04-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

            Backport from mainline
            2020-04-02  Jakub Jelinek  <jakub@redhat.com>

            PR target/94435
            * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): =
For
            y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to
SImode.

            * gcc.target/aarch64/pr94435.c: New test.=