From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 4706E388C020; Mon, 29 Jun 2020 02:04:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4706E388C020 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1593396259; bh=oIK/arvXHhJQESSX2cVT5yfiRX2bUFaVo4JaYtm2Vas=; h=From:To:Subject:Date:In-Reply-To:References:From; b=ioezIPkItq5GR9UlTgtnmHtnx4JBtqzLeurDg+Ppc/fZ1ZFxLMX6V0qBLOum8BJqI CduaeMmbUVbscRUHLIHAk7gMZk/c/uasMsVsOW/DswkXUNkIIYw8CygYNsLvlFI1xE qqPSmVIQbjoQvmF9D9MhBTkKdpTJZBE7pUAVWuZo= From: "xiezhiheng at huawei dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/94442] [10/11 regression] Redundant loads/stores emitted at -O3 Date: Mon, 29 Jun 2020 02:04:19 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 10.0 X-Bugzilla-Keywords: alias, missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: xiezhiheng at huawei dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 10.2 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 29 Jun 2020 02:04:19 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94442 --- Comment #6 from xiezhiheng at huawei dot com --- I'm trying to modify get_inner_reference to handle the case for MEM[ptr, off]. I extract the "off" and add it to the recorded offset, then I build a MEM[ptr, 0] and return it later. Like this } exp =3D TREE_OPERAND (TREE_OPERAND (exp, 0), 0); } + else if (TREE_CODE (TREE_OPERAND (exp, 0)) =3D=3D SSA_NAME) + { + tree off =3D TREE_OPERAND (exp, 1); + if (!integer_zerop (off)) + { + poly_offset_int boff =3D mem_ref_offset (exp); + boff <<=3D LOG2_BITS_PER_UNIT; + bit_offset +=3D boff; + + exp =3D build2 (MEM_REF, TREE_TYPE (exp), + TREE_OPERAND (exp, 0), + build_int_cst (TREE_TYPE (off), 0)); + } + } goto done; default: Assembly with the patch looks like: .L6: ldp q3, q2, [x0, 64] add w2, w2, 1 sqadd v1.16b, v1.16b, v3.16b sqadd v0.16b, v0.16b, v2.16b sqadd v1.16b, v1.16b, v3.16b sqadd v0.16b, v0.16b, v2.16b sqadd v3.16b, v3.16b, v1.16b sqadd v2.16b, v2.16b, v0.16b sqadd v1.16b, v1.16b, v3.16b sqadd v0.16b, v0.16b, v2.16b sqadd v1.16b, v1.16b, v3.16b sqadd v0.16b, v0.16b, v2.16b sqadd v3.16b, v3.16b, v1.16b sqadd v2.16b, v2.16b, v0.16b sqadd v1.16b, v1.16b, v3.16b sqadd v0.16b, v0.16b, v2.16b sqadd v5.16b, v1.16b, v3.16b sqadd v4.16b, v0.16b, v2.16b stp q1, q0, [x0] sqadd v3.16b, v3.16b, v5.16b sqadd v2.16b, v2.16b, v4.16b sqadd v1.16b, v1.16b, v3.16b sqadd v0.16b, v0.16b, v2.16b stp q3, q2, [x0, 64] stp q1, q0, [x0, 32] cmp w1, w2 bne .L6=