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From: "xiezhiheng at huawei dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug tree-optimization/94442] [10/11 regression] Redundant
 loads/stores emitted at -O3
Date: Wed, 06 May 2020 08:00:34 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94442

--- Comment #4 from xiezhiheng at huawei dot com ---
(In reply to Richard Biener from comment #3)
> So I wonder why
>=20
>   a$vect_s8$0_4 =3D MEM[(const struct __m256i &)output_5(D) + 32].vect_s8=
[0];=20=20
>=20
> necessarily emits two RTL insns.  It's likely because get_inner_reference
> will not see through MEM[output_5(D) + 32] but records an extra offset
> from the component-ref which we fail to fold into the MEM generated by
> expansion of the MEM base.

Indeed, get_inner_reference only handles the decl for MEM[&decl, off]
  case MEM_REF:
    /* Hand back the decl for MEM[&decl, off].  */
    if (TREE_CODE (TREE_OPERAND (exp, 0)) =3D=3D ADDR_EXPR)
      {
        tree off =3D TREE_OPERAND (exp, 1);
        if (!integer_zerop (off))
          {
            poly_offset_int boff =3D mem_ref_offset (exp);
            boff <<=3D LOG2_BITS_PER_UNIT;
            bit_offset +=3D boff;
          }
        exp =3D TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
      }
    goto done;

In
  MEM[(const struct __m256i &)output_5(D) + 32].vect_s8[0];
output_5 is a SSA_NAME.
So maybe we could expand to handle the situation like MEM[decl, off]=