[Bug target/94461] New: [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[Bug target/94461] New: [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

            Bug ID: 94461
           Summary: [10 Regression] ICE: in extract_insn, at recog.c:2294
                    with __builtin_ia32_pmuludq() and -mno-sse2
           Product: gcc
           Version: 10.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---
              Host: x86_64-pc-linux-gnu

Created attachment 48174
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48174&action=edit
reduced testcase

Compiler output:
$ x86_64-pc-linux-gnu-gcc -mno-sse2 testcase.c     
testcase.c: In function 'foo':
testcase.c:8:1: error: unrecognizable insn:
    8 | }
      | ^
(insn 7 6 10 2 (set (reg:V1DI 82 [ _2 ])
        (mult:V1DI (zero_extend:V1DI (vec_select:V1SI (reg:V2SI 84)
                    (parallel [
                            (const_int 0 [0])
                        ])))
            (zero_extend:V1DI (vec_select:V1SI (reg:V2SI 84)
                    (parallel [
                            (const_int 0 [0])
                        ]))))) "testcase.c":7:10 -1
     (nil))
during RTL pass: vregs
testcase.c:8:1: internal compiler error: in extract_insn, at recog.c:2294
0x6d36a8 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /repo/gcc-trunk/gcc/rtl-error.c:108
0x6d372b _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /repo/gcc-trunk/gcc/rtl-error.c:116
0x6c2b11 extract_insn(rtx_insn*)
        /repo/gcc-trunk/gcc/recog.c:2294
0xca6a83 instantiate_virtual_regs_in_insn
        /repo/gcc-trunk/gcc/function.c:1607
0xca6a83 instantiate_virtual_regs
        /repo/gcc-trunk/gcc/function.c:1977
0xca6a83 execute
        /repo/gcc-trunk/gcc/function.c:2026
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

Compiler output (gcc-9):
$ x86_64-pc-linux-gnu-gcc -mno-sse2 testcase.c
testcase.c: In function 'foo':
testcase.c:7:10: error: '__builtin_ia32_pmuludq' needs isa option -msse2 -mmmx
    7 |   return __builtin_ia32_pmuludq (a, a);
      |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~


$ x86_64-pc-linux-gnu-gcc -v                   
Using built-in specs.
COLLECT_GCC=/repo/gcc-trunk/binary-latest-amd64/bin/x86_64-pc-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/repo/gcc-trunk/binary-trunk-r10-7481-20200331151333-gf14b41d2712-checking-yes-rtl-df-extra-amd64/bin/../libexec/gcc/x86_64-pc-linux-gnu/10.0.1/lto-wrapper
Target: x86_64-pc-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--with-cloog --with-ppl --with-isl --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=x86_64-pc-linux-gnu
--with-ld=/usr/bin/x86_64-pc-linux-gnu-ld
--with-as=/usr/bin/x86_64-pc-linux-gnu-as --disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r10-7481-20200331151333-gf14b41d2712-checking-yes-rtl-df-extra-amd64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 10.0.1 20200331 (experimental) (GCC)

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #1 from Zdenek Sojka <zsojka at seznam dot cz> ---
This seems to affect sse3 intrinsics as well:
$ gcc-10 testcase-min0.i -w
testcase-min0.i: In function 'foo0':
testcase-min0.i:15:1: error: unrecognizable insn:
   15 | }
      | ^
(insn 28 27 29 2 (set (reg:V2SI 83 [ _2 ])
        (vec_concat:V2SI (minus:SI (vec_select:SI (reg:V2SI 95)
                    (parallel [
                            (const_int 0 [0])
                        ]))
                (vec_select:SI (reg:V2SI 95)
                    (parallel [
                            (const_int 1 [0x1])
                        ])))
            (minus:SI (vec_select:SI (reg:V2SI 82 [ _1 ])
                    (parallel [
                            (const_int 0 [0])
                        ]))
                (vec_select:SI (reg:V2SI 82 [ _1 ])
                    (parallel [
                            (const_int 1 [0x1])
                        ]))))) "testcase-min0.i":14:20 -1
     (nil))
during RTL pass: vregs
testcase-min0.i:15:1: internal compiler error: in extract_insn, at recog.c:2294
0x6d36a8 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /repo/gcc-trunk/gcc/rtl-error.c:108
0x6d372b _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /repo/gcc-trunk/gcc/rtl-error.c:116
0x6c2b11 extract_insn(rtx_insn*)
        /repo/gcc-trunk/gcc/recog.c:2294
0xca6a83 instantiate_virtual_regs_in_insn
        /repo/gcc-trunk/gcc/function.c:1607
0xca6a83 instantiate_virtual_regs
        /repo/gcc-trunk/gcc/function.c:1977
0xca6a83 execute
        /repo/gcc-trunk/gcc/function.c:2026
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

$ gcc-9 testcase-min0.i -w
testcase-min0.i: In function 'foo0':
testcase-min0.i:14:20: error: '__builtin_ia32_phsubd' needs isa option -mssse3
-mmmx
   14 |  v64s32 v64s32_3 = __builtin_ia32_psrld(__builtin_ia32_phsubd
(v64s32_2, __builtin_ia32_pandn(v64s32_1, v64s32_2)), v64s32_0);
      |                   
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Applies at least to __builtin_ia32_psubd() and __builtin_ia32_psubb() as well.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Target Milestone|---                         |10.0
                 CC|                            |jakub at gcc dot gnu.org
   Last reconfirmed|                            |2020-04-02
             Status|UNCONFIRMED                 |NEW

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Started with r10-457-g45641b316a7b2c9bdf1d7807631731457b8cc0f1

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|P3                          |P1

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[ubizjak at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |hjl.tools at gmail dot com

--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
It looks to me that the fix for PR90497 is not entirely correct, because it
allows to bypass builtins that have additional SSE* restrictions.

The following test also fails with -mmmx -msse -mno-sse2 (or -m32):

ttt.c: In function ‘foo’:
ttt.c:8:1: error: unrecognizable insn:
    8 | }
      | ^
(insn 9 8 10 2 (set (reg:V2DF 85)
        (float:V2DF (reg:V2SI 86))) "ttt.c":7:10 -1
     (nil))
during RTL pass: vregs
ttt.c:8:1: internal compiler error: in extract_insn, at recog.c:2294
0x6ae303 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /home/uros/git/gcc/gcc/rtl-error.c:108
0x6ae31f _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /home/uros/git/gcc/gcc/rtl-error.c:116
0x6ac907 extract_insn(rtx_insn*)
        /home/uros/git/gcc/gcc/recog.c:2294
0xa8d885 instantiate_virtual_regs_in_insn
        /home/uros/git/gcc/gcc/function.c:1607
0xa8d885 instantiate_virtual_regs
        /home/uros/git/gcc/gcc/function.c:1977
0xa8d885 execute
        /home/uros/git/gcc/gcc/function.c:2026

CC author.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[hjl.tools at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #4 from H.J. Lu <hjl.tools at gmail dot com> ---
Why do we have

define_expand "sse2_umulv1siv1di3"
  [(set (match_operand:V1DI 0 "register_operand")
        (mult:V1DI
          (zero_extend:V1DI
            (vec_select:V1SI
              (match_operand:V2SI 1 "nonimmediate_operand")
              (parallel [(const_int 0)])))
          (zero_extend:V1DI
            (vec_select:V1SI
              (match_operand:V2SI 2 "nonimmediate_operand")
              (parallel [(const_int 0)])))))]
  "TARGET_SSE2"
  "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")

i386-builtin.def:BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ,
UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI)

sse2_umulv1siv1di3 isn't available with MMX.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[hjl.tools at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #5 from H.J. Lu <hjl.tools at gmail dot com> ---
The following ones:

BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_sse2_cvtpd2pi,
"__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int)
V2SI_FTYPE_V2DF)
BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_sse2_cvttpd2pi,
"__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int)
V2SI_FTYPE_V2DF)
BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_sse2_cvtpi2pd,
"__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int)
V2DF_FTYPE_V2SI)
BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ,
UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv8qi2,
"__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv4hi2,
"__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv2si2,
"__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW,
UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD,
UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW,
UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW,
UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD,
UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW,
UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW,
UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW,
UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB,
UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB,
UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW,
UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND,
UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI)
BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0,
CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR,
UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT)

have the same problem.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[hjl.tools at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #6 from H.J. Lu <hjl.tools at gmail dot com> ---
(In reply to Uroš Bizjak from comment #3)
> It looks to me that the fix for PR90497 is not entirely correct, because it
> allows to bypass builtins that have additional SSE* restrictions.
> 
> The following test also fails with -mmmx -msse -mno-sse2 (or -m32):
> 
> ttt.c: In function ‘foo’:
> ttt.c:8:1: error: unrecognizable insn:
>     8 | }
>       | ^
>

Where is the test?

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
As I said in PR90497, the PR79565/PR82483 changes made SSE{,2,3} | MMX in
i386-builtins.def mean that both the SSE* and MMX must be enabled, rather than
either one or the other.  Now, with MMX_WITH_SSE, if the V2SI etc. modes are
also enabled, we can treat that as SSE* and (MMX or MMX_WITH_SSE), but
certainly shouldn't enable it if just MMX is enabled and SSE* is not.
Now, if there are any builtins that have been added or changed in the
MMX_WITH_SSE changeset that want something else (like either MMX or SSE*), then
we'll need a different representation.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #8 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
So, I believe the r10-400-gecfdb16c54ad06ac23193e5de292fc71e5958526 change has
been incorrect.
We should revert those i386-builtin.def changes, and instead treat builtins
with sole OPTION_MASK_ISA_MMX (and nothing else) as being enabled also if
TARGET_MMX_WITH_SSE, not just with TARGET_MMX.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[hjl.tools at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #9 from H.J. Lu <hjl.tools at gmail dot com> ---
(In reply to Jakub Jelinek from comment #8)
> So, I believe the r10-400-gecfdb16c54ad06ac23193e5de292fc71e5958526 change
> has been incorrect.
> We should revert those i386-builtin.def changes, and instead treat builtins
> with sole OPTION_MASK_ISA_MMX (and nothing else) as being enabled also if
> TARGET_MMX_WITH_SSE, not just with TARGET_MMX.

The problem is OPTION_MASK_ISA_MMX is used for 2 different purposes:

1. Enable MMX registers.
2. Enable MMX ISA.

pcmpeq is an MMX insn, but 128bit pcmpeq is in SSE2, not SSE.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #10 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Created attachment 48182
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48182&action=edit
gcc10-pr94461-wip.patch

What I'm proposing is essentially this patch (+ the testcase of course).
Or, instead of isa |= OPTION_MASK_ISA_MMX; we could if OPTION_MASK_ISA_MMX is
set in bisa and not set in isa and TARGET_MMX_WITH_SSE is set clear
OPTION_MASK_ISA_MMX and set OPTION_MASK_ISA_SSE2.  The difference between that
would be just in what we print as suggestion on what the builtin needs.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #11 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
It doesn't work as is though, looking at it now.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[hjl.tools at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #12 from H.J. Lu <hjl.tools at gmail dot com> ---
Created attachment 48186
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48186&action=edit
An incomplete patch

Jakub, this is an incomplete patch with 2 testcases.  Can you take it over?
I will fix PR 94467.  Thanks.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #13 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Created attachment 48187
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48187&action=edit
gcc10-pr94461-wip2.patch

Here is what I have right now and it passes make check-{gcc,c++-all}
RUNTESTFLAGS='--target_board=unix\{-m32,-m64\} i386.exp'.  Just writing
ChangeLog now.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
  Attachment #48182|0                           |1
        is obsolete|                            |
  Attachment #48187|0                           |1
        is obsolete|                            |
             Status|NEW                         |ASSIGNED
           Assignee|hjl.tools at gmail dot com         |jakub at gcc dot gnu.org

--- Comment #14 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Created attachment 48188
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=48188&action=edit
gcc10-pr94461.patch

Full patch (though tested only with i386.exp so far).

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

--- Comment #15 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:a13d6ec867e750169af95649235a6681f410464a

commit r10-7543-ga13d6ec867e750169af95649235a6681f410464a
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Fri Apr 3 20:33:17 2020 +0200

    i386: Fix up handling of OPTION_MASK_ISA_MMX builtins [PR94461]

    In https://gcc.gnu.org/ml/gcc-patches/2017-10/msg00576.html the builtin
    handling was changed so that OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE
    etc. in i386-builtin.def means we require both mmx and sse, not just one of
    those, and later on for other option combinations very similar rule has
    been clarified, with a few exceptions that ix86_expand_builtin lists
    (SSE | 3DNOW_A, SSE4_2 | CRC32 and FMA | FMA4 are one or the other).
    The above mentioned patch also added OPTION_MASK_ISA_MMX to a few insns
    that in the ISA documents are documented e.g. only requiring SSE2 or SSSE3
    etc. CPUID, but because those builtins take or return V2SI or similar
    MMX-ish arguments, we can't really support those builtins in functions that
    have MMX disabled.
    Now, during the TARGET_MMX_WITH_SSE changes,
    https://gcc.gnu.org/ml/gcc-patches/2019-02/msg01479.html
    and
    https://gcc.gnu.org/ml/gcc-patches/2019-05/msg01084.html
    actually changed this; it added | OPTION_MASK_ISA_SSE2 to builtins
    that were formerly OPTION_MASK_ISA_MMX only, but didn't touch the builtins
    that were already using OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX
    for something different (both options must be enabled).
    This causes e.g. ICE on the following testcase, because the builtins are
    now enabled even with just -mmmx -mno-sse2, even when they (those changed
in
    2017) require SSE2.
    The following patch instead reverts the above two 2019-ish changes (except
    for header/testsuite changes), and instead treats OPTION_MASK_ISA_MMX
    requirement in bdesc/.isa specially, as being satisfied by either
    TARGET_MMX (no changes really needed for that), or by TARGET_MMX_WITH_SSE.
    This achieves what the two 2019-ish patches want to do, that the
    OPTION_MASK_ISA_MMX only builtins are enabled not just with -mmmx, but also
    with -m64 -msse2, and for the other builtins that require MMX and something
    else will either require -mmmx and that some other ISA, or -m64 -msse2 and
    that other ISA, but -mmmx will not enable builtins that need something more
    than OPTION_MASK_ISA_MMX only.
    The i386-builtins.c changes that aren't reversion of the two patches try to
    make sure that in .isa we still record OPTION_MASK_ISA_MMX for builtins
that
    have that requirement, so that it is in the end only ix86_expand_builtin
    that decides if the builtin is ok or not and the rest of code just decides
    if it is the right time to declare the builtin already or if it should be
    deferred.

    2020-04-03  Jakub Jelinek  <jakub@redhat.com>

            PR target/94461
            * config/i386/i386-expand.c (ix86_expand_builtin): If
            TARGET_MMX_WITH_SSE without TARGET_MMX and bisa contains
            OPTION_MASK_ISA_MMX, clear OPTION_MASK_ISA_MMX and set
            OPTION_MASK_ISA_SSE2 in bisa.  Revert 2019-05-17 and 2019-05-15
            changes.
            * config/i386/i386-builtins.c (def_builtin): If mask includes
            OPTION_MASK_ISA_MMX and TARGET_MMX_WITH_SSE, consider it satisfied.
            (ix86_add_new_builtins): For TARGET_64BIT, consider
            OPTION_MASK_ISA_SSE2 enabled in isa as satisfying
OPTION_MASK_ISA_MMX
            requirement.
            (ix86_init_tm_builtins): If TARGET_MMX_WITH_SSE consider
            OPTION_MASK_ISA_MMX as satisfied.
            (bdesc_tm): Revert 2019-05-15 changes.
            (ix86_init_mmx_sse_builtins): Likewise.
            * config/i386/i386-builtin.def: Likewise.

            * gcc.target/i386/pr94461.c: New test.

[Bug target/94461] [10 Regression] ICE: in extract_insn, at recog.c:2294 with __builtin_ia32_pmuludq() and -mno-sse2

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94461

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #16 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed.