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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/94494] gcc-10 unrecognizable insn
Date: Fri, 10 Apr 2020 22:14:24 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94494

Uro=C5=A1 Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|WAITING                     |ASSIGNED
   Target Milestone|---                         |9.4
           Assignee|unassigned at gcc dot gnu.org      |ubizjak at gmail do=
t com

--- Comment #4 from Uro=C5=A1 Bizjak <ubizjak at gmail dot com> ---
Confirmed, fails with -O2 -ftree-vectorize -m32 -msse -mno-sse2.

The compiler generates SSE2 instruction with -msse.

Backtrace:

(gdb) bt
#0  0x0000000001644c80 in gen_sse2_lshrv1ti3(rtx_def*, rtx_def*, rtx_def*) =
()
at ./genrtl.h:39
#1  0x00000000013a493f in emit_reduc_half (i=3D128, src=3D0x7fffea97e870,
dest=3D0x7fffea985f18)
    at /home/uros/git/gcc/gcc/config/i386/i386-expand.c:14870
#2  ix86_expand_reduc (fn=3Dfn@entry=3D0x160ac80 <gen_smaxv4si3(rtx_def*, r=
tx_def*,
rtx_def*)>, dest=3Ddest@entry=3D0x7fffea985f00,=20
    in=3Din@entry=3D0x7fffea97e870) at
/home/uros/git/gcc/gcc/config/i386/i386-expand.c:14977
#3  0x00000000016cec5d in gen_reduc_smax_scal_v4si (operand0=3D0x7fffea97e6=
00,
operand1=3D0x7fffea97e870)
    at /home/uros/git/gcc/gcc/config/i386/sse.md:2746
#4  0x0000000000eeb3e9 in maybe_expand_insn (ops=3Dops@entry=3D0x7fffffffd8=
60,
nops=3Dnops@entry=3D2,=20
    icode=3Dicode@entry=3DCODE_FOR_reduc_smax_scal_v4si) at
/home/uros/git/gcc/gcc/optabs.c:7508
#5  expand_insn (icode=3Dicode@entry=3DCODE_FOR_reduc_smax_scal_v4si,
nops=3Dnops@entry=3D2, ops=3Dops@entry=3D0x7fffffffd860)
    at /home/uros/git/gcc/gcc/optabs.c:7508

REDUC_SSE_SMINMAX_MODE mode iterator allows V4SI, V8HI and V16QI modes for =
SSE,
but we have:

    case E_V16QImode:
    case E_V8HImode:
    case E_V4SImode:
    case E_V2DImode:
      d =3D gen_reg_rtx (V1TImode);
      tem =3D gen_sse2_lshrv1ti3 (d, gen_lowpart (V1TImode, src),
                                GEN_INT (i / 2));
      break;

in i386-expand.c/emit_reduc_half.

Patch in testing:

--cut here--
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 8f5902292c6..d978e2aa256 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -2733,8 +2733,8 @@
 ;; Modes handled by reduc_sm{in,ax}* patterns.
 (define_mode_iterator REDUC_SSE_SMINMAX_MODE
   [(V4SF "TARGET_SSE") (V2DF "TARGET_SSE")
-   (V2DI "TARGET_SSE4_2") (V4SI "TARGET_SSE") (V8HI "TARGET_SSE")
-   (V16QI "TARGET_SSE")])
+   (V4SI "TARGET_SSE2") (V8HI "TARGET_SSE2") (V16QI "TARGET_SSE2")
+   (V2DI "TARGET_SSE4_2")])

 (define_expand "reduc_<code>_scal_<mode>"
   [(smaxmin:REDUC_SSE_SMINMAX_MODE
--cut here--=