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Subject: [Bug target/94538] [9/10/11 Regression] ICE: in
 extract_constrain_insn_cached, at recog.c:2223 (insn does not satisfy its
 constraints) with -mcpu=cortex-m23 -mslow-flash-data
Date: Mon, 24 Aug 2020 09:09:19 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D94538

--- Comment #20 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:259d072067997ab8f55afcf735c91b6740fd0425

commit r11-2818-g259d072067997ab8f55afcf735c91b6740fd0425
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Wed Aug 19 09:02:21 2020 +0000

    arm: Fix -mpure-code support/-mslow-flash-data for armv8-m.base [PR9453=
8]

    armv8-m.base (cortex-m23) has the movt instruction, so we need to
    disable the define_split to generate a constant in this case,
    otherwise we get incorrect insn constraints as described in PR94538.

    We also need to fix the pure-code alternative for thumb1_movsi_insn
    because the assembler complains with instructions like
    movs r0, #:upper8_15:1234
    (Internal error in md_apply_fix)
    We now generate movs r0, 4 instead.

    2020-08-24  Christophe Lyon  <christophe.lyon@linaro.org>

            PR target/94538
            gcc/
            * config/arm/thumb1.md: Disable set-constant splitter when
            TARGET_HAVE_MOVT.
            (thumb1_movsi_insn): Fix -mpure-code
            alternative.

            PR target/94538
            gcc/testsuite/
            * gcc.target/arm/pure-code/pr94538-1.c: New test.
            * gcc.target/arm/pure-code/pr94538-2.c: New test.=